Table of Contents
Advertisement
®
Intel
855GME Chipset and Intel
Layout Checklist
®
Table 149. Intel
855GME Chipset GMCH Layout Checklist (Sheet 4 of 6)
Checklist Items
DDR VTT
Decoupling
General
Guidelines
BCLK
BCLK#
310
®
6300ESB ICH Embedded Platform Design Guide
Recommendations
• Decouple VTT termination rail using one
0603 0.1 µF capacitor per two DDR
signals.
• Spread out placement across the VTT
termination rail, connecting directly to the
rail, so that each parallel termination
resistor is within 100 mils of one of these
high-frequency capacitors.
• Each ground via should be as close to the
associated cap pad as possible, within 25
mils and with as thick a trace as possible.
• Also, place one 4.7 µF ceramic capacitor
on each end of the termination island, and
place one 4.7 µF ceramic capacitor near
the center of the termination island.
• Low frequency bulk decoupling
requirements at the VTT termination rail
should be met with (4) 470 µF caps placed
evenly across the VTT rail, including one
cap at each end.
Hub Interface
• Route hub interface data and strobes with
trace impedance 55 Ω ± 15% using 2:1
spacing and VSS reference.
• Route hub interface strobe and its
complement as a differential pair, length
matched within ± 10 mils.
• Maximum length for both data and strobe
signals is 6 inches.
• Hub interface data and strobe signals are
routed on the same layer, transitioning
together when a layer change is required.
• Keep layer changes to a minimum, using
only 2 vias per net.
Clocks and Reset Signals
• For a detailed discussion on this item, see
Section
11.2.1.
• The differential host clock pair should be
length matched to ± 10 mils and to the
processor BCLK/BCLK# pair within
± 20 mils overall (match L1 segments to
± 10 mils across all pairs).
• Route as strip-line traces 4/7 mils spacing
(except as allowed for pin escapes).
• Total length range is 2 to 8.5 inches.
Comments
• Refer to
Section 4.8.1.3
for more
information.
• Refer to
Section 8.1
for detailed
routing recommendations.
• The platform design guide example
references routing guidelines for the
8-bit Hub Interface using enhanced
(parallel) termination.
• Refer to host clock group routing
guidelines detailed in
Section
• Refer to Chapter 10 for detailed
breakdown of all system clock
routing recommendations.
11.2.1.
Advertisement
Table of Contents
