Generic Connector Model - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
Figure 80. DVO Enabled Simulation Model
All signals shall be routed as striplines (inner layers).All signals in a signal group shall be routed on
the same layer. Routing studies have shown that these guidelines may be met. The trace length and
trace spacing requirements must not be violated by any signal. Trace length mismatch for all
signals within a signal group shall be as close to ± 100 mils with respect to the strobe clocks as
possible to provide optimal timing margin.
summary.
Table 55. DVO Enabled Routing Guideline Summary
Signal
DVO Timing
Domain
For DVO module case, the simulation model is the same as
the same as in
For multiplexed design, more conservative length mismatch (± 0.1 inches) is adopted.
6.4.1.1

Generic Connector Model

Figure 81
implementation. This is only for reference. The actual connector may have different parasitic
values. Designs using this approach need to be simulated first.
Figure 81. Generic Module Connector Parasitic Model
DVOB &
DVOC I/F
GMCH
Maximum
Trace Width
Length
L1=4 in
L2=2 in
Table 55; each strobe pair must be separated from other signals by at least 12 mils.
depicts the generic connector model used in simulation for flexible DVO
Motherboard
C
1
January 2007
®
6300ESB ICH Embedded Platform Design Guide
Integrated Graphics Display Port
L1 L2
tDVb, tDVa tDVb, tDVa,
tDSu, tDh tDSu, tDh
Generic
Connector
Table 55 depicts DVO enabled routing guideline
Trace Spacing
4 mils 8 mils
Figure 80
R L
2.5nH
20mΩ
2.21 pF C
Connector
with
DVO
module
Length
Notes
Mismatch
± 100 mils
and the routing guideline is
Module
2.21 pF
2
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