Topologies And Routing Guidelines; Clock Signals - Sck[5:0], Sck[5:0]; Clock Topology Diagram - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
process of adjusting package length variation across a signal group. Of course, there is some
overlap in that both affect the target length of an individual signal. Intel recommends that the initial
route be completed based on the length matching formulas in conjunction with nominal package
lengths and that package length compensation be performed as secondary operation where
required.
5.4

Topologies and Routing Guidelines

The Intel 855GME chipset's Double Data Rate (DDR) SDRAM system memory interface
implements the low swing, high-speed, terminated SSTL_2 topology. This section contains
information related to the recommended interconnect topologies and routing guidelines for each of
the signal groups that comprise the DDR interface. When implemented as defined, these guidelines
provide a robust DDR solution on an Intel 855GME chipset-based design. The first group to be
presented are the clocks, because most of the signal groups have length formulas that are based on
clock length.
5.4.1 Clock Signals – SCK[5:0], SCK[5:0]#
The clock signal group includes the differential clock pairs SCK[5:0]/SCK[5:0]#. The GMCH
generates and drives these differential clock signals required by the DDR interface; therefore, no
external clock driver is required for the DDR interface. The GMCH only supports unbuffered DDR
DIMMs, three differential clock pairs are routed to each DIMM connector.
the clock signal mapping.
Table 29. Clock Signal Mapping
SCK[2:0]/SCK[2:0]#
SCK[5:3]/SCK[5:3]#
5.4.2

Clock Topology Diagram

The 82855GME provides six differential clock output pairs, or three clock pairs per DIMM socket.
The motherboard clock routing topology is shown in
Section 5.4.3
routed as closely-coupled differential pairs over the entire length. Spacing to other DDR signals
shall not be less than 20 mils. Isolation spacing to non-DDR signals shall be 25 mils.
Signal
for detailed length and spacing rules for each segment. The clock signals shall be
January 2007
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6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
Relative To
DIMM0
DIMM1
Figure 64. Refer to the routing guidelines in
Table 29 summarizes
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