Intel 855GME Design Manual page 4

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Intel 855GME Chipset and Intel
4.1.5.2
4.1.5.3
4.1.5.4
4.1.5.5
4.1.5.6
4.1.5.7
4.1.6 Pentium
4.1.6.1
4.1.7 Pentium
Chipset GMCH (82855GME) Host Clock Signals.................................................. 66
4.1.8 Pentium
Routing Recommendations ................................................................................... 67
4.1.9 AGTL+ I/O Buffer Compensation........................................................................... 69
4.1.9.1
4.1.10 Pentium
4.1.11 Pentium
Design Recommendations..................................................................................... 74
4.1.12 PLL Voltage Design for Low Voltage Intel
Processors on 90 nm process with 2 MB L2 Cache .............................................. 74
4.2 Intel System Validation Debug Support .............................................................................. 75
4.2.1 ITP Support............................................................................................................ 75
4.2.1.1
4.2.1.2
4.2.2 Pentium
4.2.2.1
4.2.2.2
4.2.3 Intel
Analyzer Trigger (ODLAT) Support ....................................................................... 76
4.3 Onboard Debug Port Routing Guidelines ........................................................................... 77
4.3.1 Recommended Onboard ITP700FLEX Implementation ........................................ 77
4.3.1.1
4.3.1.2
4.3.1.3
4.3.1.4
4.3.2 Recommended ITP Interposer Debug Port Implementation.................................. 84
4.3.2.1
4.3.2.2
4.3.3 Logic Analyzer Interface (LAI) ............................................................................... 85
4.3.3.1
4.3.3.2
4.3.4 Processor Phase Lock Loop (PLL) Design Guidelines.......................................... 86
4.3.4.1
4.3.4.2
4.3.4.3
4.3.5 Intel
4.3.6 Thermal Power Dissipation.................................................................................... 89
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4.4 Intel Pentium
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6300ESB ICH Embedded Platform Design Guide
Topology 1B: Open Drain (OD) Signals Driven by the Intel
Pentium M/Celeron M Processor - FERR# and THERMTRIP# ............ 59
Topology 1C: Open Drain (OD) Signals Driven by the Intel
Pentium M/Celeron M Processor - PROCHOT# ................................... 60
Topology 2A: Open Drain (OD) Signals Driven by AND Gate-
PWRGOOD............................................................................................ 61
Topology 2B: CMOS Signals Driven by 6300ESB-LINT0/INTR,
LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK#................... 62
Topology 3: CMOS Signals Driven by 6300ESB
to CPU and FWH - INIT# ...................................................................... 62
Voltage Translation Logic ...................................................................... 63
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M/Celeron M Processor RESET# Signal............................................. 64
Processor RESET# Routing Example ................................................... 65
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M/Celeron M Processor and Intel 855GME
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M/Celeron M Processor GTLREF Layout and
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Pentium M/Celeron
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M/Celeron M Processor System Bus Strapping .................................. 72
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M/Celeron M Processor VCCSENSE/VSSSENSE
Background/Justification ........................................................................ 75
Implementation ...................................................................................... 75
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M/Celeron M Processor Logic Analyzer Support (FSB LAI)................ 76
Background/Justification ........................................................................ 76
Implementation ...................................................................................... 76
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Pentium M/Celeron
ITP Signal Routing Guidelines ............................................................... 77
ITP Signal Routing Example .................................................................. 81
ITP_CLK Routing to ITP700FLEX Connector........................................ 82
ITP700FLEX Design Guidelines for Production Systems ...................... 83
ITP_CLK Routing to ITP Interposer ....................................................... 84
ITP Interposer Design Guidelines for Production Systems.................... 85
Mechanical Considerations.................................................................... 86
Electrical Considerations ....................................................................... 86
Processor PLL Power Delivery .............................................................. 86
Processor PLL Voltage Supply Power Sequencing ............................... 88
Processor PLL Decoupling Requirements ............................................. 88
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Pentium M/Celeron
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M/Celeron M Processor Decoupling Recommendations........................ 90
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M Processor AGTL+ I/O Buffer Compensation.. 69
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Pentium
M Processor On-Die Logic
M Processor Power Status Indicator (PSI#) Signal . 89
M