Intel 855GME Design Manual page 6

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Intel 855GME Chipset and Intel
5.4.3.3
5.4.4 Data Signals - SDQ[71:0], SDM[8:0], SDQS[8:0] ............................................... 130
5.4.4.1
5.4.4.2
5.4.4.3
5.4.4.4
5.4.4.5
5.4.5 Control Signals - SCKE[3:0], SCS[3:0]# ............................................................. 138
5.4.5.1
5.4.5.2
5.4.5.3
5.4.5.4
5.4.6 Command Signals - SMA[12:6,3,0], SBA[1:0],
SRAS#, SCAS#, SWE# ....................................................................................... 142
5.4.6.1
5.4.6.2
5.4.6.3
5.4.6.4
5.4.7 CPC Signals - SMA[5,4,2,1], SMAB[5,4,2,1] ...................................................... 146
5.4.7.1
5.4.7.2
5.4.7.3
5.4.7.4
5.4.8 Feedback - RCVENOUT#, RCVENIN#............................................................... 150
5.5 ECC Guidelines ................................................................................................................ 150
5.5.1 GMCH ECC Functionality .................................................................................... 150
5.5.2 DRAM Clock Flexibility ........................................................................................ 151
6 Integrated Graphics Display Port............................................................................................. 153
6.1 Analog RGB/CRT Guidelines ........................................................................................... 153
6.1.1 RAMDAC/Display Interface ................................................................................. 153
6.1.2 Reference Resistor (RSET) ................................................................................. 153
6.1.3 RAMDAC Board Design Guidelines .................................................................... 154
6.1.4 DAC Routing Guidelines...................................................................................... 155
6.1.5 DAC Power Requirements................................................................................... 157
6.1.6 HSYNC and VSYNC Design Considerations....................................................... 158
6.1.7 DDC and I
6.2 LVDS Transmitter Interface .............................................................................................. 158
6.2.1 Length Matching Constraints ............................................................................... 159
6.2.1.1
6.2.2 LVDS Routing Guidelines .................................................................................... 160
6.3 Digital Video Out Port ....................................................................................................... 161
6.3.1 DVO Interface Signal Groups .............................................................................. 162
6.3.1.1
6.3.2 DVOB and DVOC Port Interface Routing Guidelines .......................................... 163
6.3.2.1
6.3.2.2
6.3.2.3
6.3.2.4
6.3.3 DVOB and DVOC Assumptions, Definitions, and Specifications......................... 167
6.3.4 DVOB and DVOC Simulation Method ................................................................. 167
6.4 DVOB and DVOC Port Flexible (Modular) Design............................................................ 168
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6300ESB ICH Embedded Platform Design Guide
Clock Length Package Table ............................................................... 130
Data Bus Topology .............................................................................. 131
SDQS to Clock Length Matching Requirements.................................. 133
Data to Strobe Length Matching Requirements................................... 134
SDQ to SDQS Mapping ....................................................................... 135
SDQ/SDQS Signal Package Lengths .................................................. 136
Control Signal Routing Topology ......................................................... 139
Control Signal Routing Guidelines ....................................................... 140
Control to Clock Length Matching Requirements ................................ 140
Control Group Package Length Table ................................................. 142
Command Signal Routing Topology .................................................... 142
Command Topology Routing Guidelines ............................................. 143
Command Topology Length Matching Requirements.......................... 144
Command Group Package Length Table ............................................ 146
CPC Signal Routing Topology ............................................................. 147
CPC Signal Routing Guidelines ........................................................... 148
CPC to Clock Length Matching Requirements .................................... 148
CPC Group Package Length Table ..................................................... 150
2
C Design Considerations................................................................... 158
Package Length Compensation........................................................... 159
DVO/I2C to AGP Pin Mapping ............................................................. 162
Length Mismatch Requirements .......................................................... 163
Package Length Compensation........................................................... 164
DVOB and DVOC Routing Guidelines ................................................. 165
DVOB and DVOC Port Termination..................................................... 166