Intel 855Gme Chipset Platform Power Delivery Guidelines - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
When the above criteria cannot be met by the system design,
power up. Refer to Intel
Table 23. DDR Power-Up Initialization Sequence
Voltage Description
4.8 Intel 855GME Chipset Platform Power Delivery
Guidelines
Each component is capable of generating large current swings when switching between logic high
and logic low. This condition could cause the component voltage rails to drop below specified
limits. To avoid this type of situation, ensure that the appropriate amount of bulk capacitance is
added in parallel to the voltage input pins. Intel recommends that the developer use the amount of
decoupling capacitors specified in this document to ensure the component maintains stable supply
voltages. The capacitors shall be placed as close to the package as possible. Rotate caps that sit
over power planes so that the loop inductance is minimized (see
minimizing loop inductance is to consider which voltage is on Layer 2 (power or ground) and spin
the decoupling cap with the opposite voltage toward the ball grid array (BGA). This greatly
minimizes the total loop inductance. Intel recommends that for prototype board designs, the
designer shall include pads for extra power plane decoupling caps.
Figure 51. Example for Minimizing Loop Inductance
Decoupling
Layer 1
Layer 2
Layer 3
Layer 4
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DDR 200 JEDEC Spec Addendum for more details.
Sequencing
VDDQ After or with VDD
VTT After or with VDDQ
VREF After or with VDDQ
Copper
Plane
Under BGA
Cap
GND
VIA
Current Flow to Decoupling Cap
January 2007
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6300ESB ICH Embedded Platform Design Guide
Table 23
Voltage Relationship to Avoid Latch-up
< VDD + 0.3 V
< VDDQ + 0.3 V
< VDDQ + 0.3 V
Trace
connecting
Pad to Via
GND
BGA
Ball
BALL
PWR
PAD
GND
must be adhered to during
Figure 51). The basic theory for
BGA
Substrate
PWR
BGA
Ball BALL
4.5 mils nominal
48 mils nominal
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