Dvob And Dvoc Assumptions, Definitions, And Specifications; Dvob And Dvoc Simulation Method; Dvob And Dvoc Simulations Model - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
6.3.3 DVOB and DVOC Assumptions, Definitions, and
Specifications
The source synchronous solution space consists of all designs in which the flight time mismatch
between a strobe and its associated data is less than the total allowable skew:
T = T
skew
Where T
flight data
strobe respectively.
The DVO physical interface is a point-to-point topology using 1.5 V signaling. The DVO uses a
165 MHz clock.
The flight time skew simulations reproduce all parameters that could cause a skew between two
signals, including motherboard and add-in card line lengths, effective capacitance in the buffer
models, crosstalk on each of the different interconnect combinations, data pattern dependencies,
and ISI induced skews.
6.3.4

DVOB and DVOC Simulation Method

A model for simulation purposes is shown in
Figure 78. DVOB and DVOC Simulations Model
- T
flight data flight strobe
and T are the driver-pad-to-receiver-pin flight times of the data and the
flight strobe
tDVb, tDVa
DVO I/F
GMCH
January 2007
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6300ESB ICH Embedded Platform Design Guide
Integrated Graphics Display Port
Figure 78. The DVO component is a third party-chip.
tDSu, tDh
DVOB/DVOC
Control, Data
DVO
(Device)
167