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®
Intel
855GME Chipset and Intel
System Memory Design Guidelines (DDR-SDRAM)
5.4.6.4
Command Group Package Length Table
The package length data in
signal to its associated clock reference length.
Table 39. Command Group Package Lengths
Signal
SMA[0]
SMA[3]
SMA[6]
SMA[7]
SMA[8]
SMA[9]
SMA[10]
SMA[11]
SMA[12]
SBA[0]
SBA[1]
SCAS#
SRAS#
SWE#
5.4.7
CPC Signals – SMA[5,4,2,1], SMAB[5,4,2,1]
The 82855GME control signals, SMA[5,4,2,1] and SMAB[5,4,2,1], are common clocked signals.
They are "clocked" into the DDR SDRAM devices using clock signals SCK[5:0]/SCK[5:0]#. The
GMCH drives the CPC and clock signals together, with the clocks crossing in the valid control
window. The GMCH provides one set of CPC signals per DIMM slot. Refer to
SMA and SMAB signal to DIMM mapping.
Table 40. Control Signal to DIMM Mapping
Signal
SMA[1]
SMA[2]
SMA[4]
SMA[5]
SMAB[1]
SMAB[2]
SMAB[4]
SMAB[5]
146
®
6300ESB ICH Embedded Platform Design Guide
Table 39
shall be used to match the overall length of each command
Pin Number
AC18
AD17
AD8
AD7
AC6
AC5
AC19
AD5
AB5
AD22
AD20
AC24
AC21
AD25
Relative To
DIMM Pin
DIMM0
AD14
DIMM0
AD13
DIMM0
AD11
DIMM0
AC13
DIMM1
AD16
DIMM1
AC12
DIMM1
DIMM1
AD10
Pkg Length (mils)
420
472
591
596
630
681
377
683
609
592
435
562
499
751
AF11
Table 40
for the
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