Power Checklist - Intel 855GME Design Manual

Chipset, ich embedded platform
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®
Intel
855GME Chipset and Intel
12.4.16

Power Checklist

Table 147.

Power Checklist

Checklist Items
V
3.3
CC
V
1_5
CC
V
Sus3.3
CC
V
Sus1_5
CC
V_CPU_IO
V
PLL
CC
V
HI
CC
VCCREF
V5_REF
V5_REF_Sus
V
RTC
CC
VCCA
®
6300ESB ICH Embedded Platform Design Guide
Recommendations
Use twelve 0.1 µF and four 0.01 µF
decoupling caps
Use six 0.1 µF and two 0.01 µF decoupling
caps
Use four 0.1 µF, one 0.01 µF, and one
1.0 µF decoupling cap
Use four 0.1 µF decoupling caps
The power pins should be connected to the
proper power plane for the CPU's CMOS
Compatibility Signals. Use one 0.1 µF
decoupling cap.
Use three 0.1 µF decoupling caps
Use two 0.1 µF decoupling caps
Use one 1.0 µF decoupling cap
Use one 0.1 µF decoupling cap
V5REF is the reference voltage for 5 V
tolerant inputs in the 6300ESB. V5_REF
must power up before or simultaneous to
V
3.3. It must power down after or
CC
simultaneous to V
3.3.
CC
Use one 0.1 µF decoupling cap
V5_REF_Sus is the reference voltage for 5
V tolerant inputs in the 6300ESB.
V5_REF_Sus must power up before or
simultaneous to V
Sus3.3. It must power
CC
down after or simultaneous to V
For most platforms this is not an issue
because V
Sus3.3 is usually derived from
CC
V5_REF_Sus.
Use two 0.1 µF decoupling caps, one close
to the 6300ESB, and one close to the
battery.
No clear CMOS jumper on V
CC
jumper on RTCRST# or a GPI, or use a safe
mode strapping for Clear CMOS
Use one 0.1 µF decoupling cap
January 2007
Schematic Checklist Summary
Reason/Impact
Proper connection ensures
functionality of system features
(i.e., USB 2.0)
Proper connection ensures
functionality of system features
(i.e., USB 2.0)
Sus3.3.
CC
RTC. Use a
297

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