Intel 855GME Design Manual page 132

®
Intel 855GME Chipset and Intel
System Memory Design Guidelines (DDR-SDRAM)
Table 32
Table 32. Data Signal Group Routing Guidelines
Signal Group
Motherboard Topology
Reference Plane
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Minimum Spacing to Trace Width Ratio
Minimum Isolation Spacing to non-DDR Signals
Package Length P1
Trace Length P1+ L1 – GMCH Die-Pad to Series
Termination Resistor Pad
Trace Length L2 – Series Termination Resistor Pad to
First DIMM Pad
Total Length P1+ L1+L2 – Total Length from GMCH to
First DIMM Pad
Trace Length L3 – First DIMM Pad to Last DIMM Pad
Trace Length L4 – Last DIMM Pad to Parallel
Termination Resistor Pad
Total Length P1+ L1+L2+L3 – Total Length from GMCH
to Second DIMM Pad
Series Termination Resistor (Rs)
Parallel Termination Resistor (Rt)
Maximum Recommended Motherboard Via Count Per
Signal
Length Matching Requirements
NOTES:
1. Power distribution vias from Rt to Vtt are not included in this count.
2. The overall minimum and maximum length to the DIMM must comply with clock length matching
requirements.
132
®
6300ESB ICH Embedded Platform Design Guide
presents the data signal group routing guidelines.
Parameter Definition
SDQ[71:0], SDQS[8:0], SDM[8:0]
Daisy Chain with Parallel Termination
Ground Referenced
55 Ω ± 15%
Inner layers: 4 mils
Outer layers: 5 mils
SDQ/SDM: 2:1 (e.g., 8 mil space to 4 mil trace)
SDQS: 3 to 1 (e.g., 12 mil space to 4 mil trace)
20 mils
700 mils ± 300 mils
Refer to package length for details.
Min = 2"-L2
Max = 6"-L3-L2
Max = 0.75"
Min = 2.0"
Max = 6"-L3
Min = 0.25"
Max = 2.0"
Max = 1.0"
Min = 2"+L3
Max = 6.0"
10 Ω ± 5%
56 Ω ± 5%
6
Match SDQS to SCK/SCK#
Refer to length matching Section 5.4.4.2
Figure 67.
SDQ/SDM to SDQS, to ± 25 mils, within each
byte lane.
Refer to length matching Section 5.4.4.3
Figure 68.
and
and