Gmch And Ddr Smvref Design Recommendations; Ddr Smrcomp Resistive Compensation - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
spec states a tolerance in terms of volts (e.g., VREF says ± 0.025 V), that specific voltage tolerance
shall be used, not a percentage of the measured value. Likewise, percentages shall be used where
stated.
As shown in the tables, only the 2.5 V supply has an absolute specification. The 1.25 V supply for
both VREF and VTT need to track the 2.5 V supply closely.
4.8.2.2

GMCH and DDR SMVREF Design Recommendations

There is one SMVREF pin on the GMCH that is used to set the reference voltage level for the DDR
system memory signals (SMVREF). The voltage level that needs to be supplied to this pin must be
equal to VCCSM/2. As shown in
SMVREF from the 2.5 V supply. This shall be used as the VREF signals to both the DDR memory
devices and the SMVREF signal to the GMCH. Note that SMVREF must be provided in S3.
4.8.2.3

DDR SMRCOMP Resistive Compensation

The GMCH requires a system memory compensation resistor, SMRCOMP, to adjust buffer
characteristics to specific board and operation environment characteristics. Refer to the Intel
855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH) Datasheet and
Figure 53
wide a trace as possible. It shall be a minimum of 12 mils wide and be isolated from other signals
with a minimum of 10 mils spacing.
Figure 53. GMCH SMRCOMP Resistive Compensation
The GMCH's system memory resistive compensation mechanism also requires the generation of
reference voltages to the SMVSWINGL and SMVSWINGH pins. The schematic for
SMVSWINGL and SMVSWINGH voltage generation is illustrated in
dividers with R1b = R2a = 150 Ω ± 1% and R1a = R2b = 604 Ω ± 1% generate the SMVSWINGL
and SMVSWINGH voltages. SMVSWINGL and SMVSWINGH components shall be placed
within 0.5 inches of their respective pins and connected with a 15 mil wide trace. To avoid
coupling with any other signals, maintain a minimum of 25 mils of separation to other signals.
Figure 52
for details on resistive compensation. The SMRCOMP signal shall be routed with as
60.4 Ω ±1%
SMRCOMP
January 2007
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6300ESB ICH Embedded Platform Design Guide
an OpAmp buffer is recommended to generate
+V2.5
60.4 Ω ±1%
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0.1 μ F
Figure 54. Two resistive
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