Intel 855GME Design Manual page 5

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Intel 855GME Chipset and Intel
4.4.1 Transient Response............................................................................................... 90
4.4.2 High-Frequency/Mid-Frequency and Bulk Decoupling Capacitors ........................ 91
4.4.3 Processor Core Voltage Plane and Decoupling..................................................... 91
4.4.4 Processor and GMCH VCCP Voltage Plane and Decoupling ............................. 100
4.4.5 GMCH Core Voltage Plane and Decoupling........................................................ 101
4.5 Power and Sleep State Definitions ...................................................................................101
4.6 Power Delivery Map.......................................................................................................... 103
4.7 Intel 855GME Chipset Platform Power-Up Sequence ...................................................... 105
4.7.1 GMCH Power Sequencing Requirements ........................................................... 105
4.7.2 6300ESB Power Sequencing Requirements ....................................................... 105
4.7.2.1
4.7.2.2
4.7.3 PCI-X Power Sequencing .................................................................................... 106
4.7.4 DDR Memory Power Sequencing Requirements................................................. 106
4.8 Intel 855GME Chipset Platform Power Delivery Guidelines .............................................107
4.8.1 Intel 855GME Chipset and Decoupling Guidelines.............................................. 108
4.8.1.1
4.8.1.2
4.8.1.3
4.8.2 DDR Memory Power Delivery Design Guidelines................................................ 109
4.8.2.1
4.8.2.2
4.8.2.3
4.8.2.4
4.8.2.5
4.8.3 Other GMCH Reference Voltage and Analog Power Delivery............................. 113
4.8.3.1
4.8.3.2
4.8.3.3
4.8.3.4
4.8.4 Intel
4.8.5 Power Supply PS_ON Consideration .................................................................. 119
4.8.6 Intel
4.8.7 Intel
4.8.8 Intel® 6300ESB Power Consumption .................................................................. 120
4.8.9 Intel
4.8.10 6300ESB Power Signal Decoupling ................................................................... 121
4.8.11 Hub Interface Decoupling .................................................................................... 121
4.8.12 FWH Decoupling.................................................................................................. 121
4.9 Thermal Design Power ..................................................................................................... 121
5 System Memory Design Guidelines (DDR-SDRAM) ............................................................... 123
5.1 Introduction ....................................................................................................................... 123
5.2 Length Matching and Length Formulas ............................................................................124
5.3 Package Length Compensation........................................................................................124
5.4 Topologies and Routing Guidelines .................................................................................. 125
5.4.1 Clock Signals - SCK[5:0], SCK[5:0]# .................................................................. 125
5.4.2 Clock Topology Diagram ..................................................................................... 125
5.4.3 DDR Clock Routing Guidelines............................................................................126
5.4.3.1
5.4.3.2
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6300ESB ICH Embedded Platform Design Guide
V5REF/3.3V Sequencing .....................................................................105
3.3V/1.5V Power Sequencing .............................................................. 106
GMCH VCCSM Decoupling ................................................................. 108
DDR SDRAM VDD Decoupling............................................................ 109
DDR VTT Decoupling Placement and Layout Guidelines.................... 109
2.5 V Power Delivery Guidelines .........................................................110
GMCH and DDR SMVREF Design Recommendations ....................... 111
DDR SMRCOMP Resistive Compensation.......................................... 111
DDR VTT Termination ......................................................................... 112
DDR SMRCOMP and VTT 1.25 V Supply Disable in S3/Suspend ...... 112
GMCH GTLVREF ................................................................................ 113
GMCH AGTL+ I/O Buffer Compensation .............................................115
GMCH AGTL+ Reference Voltage ....................................................... 115
GMCH Analog Power........................................................................... 116
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6300ESB Power Delivery........................................................................... 118
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6300ESB Analog Power Delivery .............................................................. 120
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6300ESB Standby Power Distribution ....................................................... 120
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6300ESB Decoupling Recommendations ..................................................120
Clock Length Matching Requirements ................................................. 127
Clock Reference Lengths.....................................................................128
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