Intel 855GME Design Manual page 12

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Intel 855GME Chipset and Intel
Figures
1 Embedded Intel® 855GME Chipset System Block Diagram ...................................................... 26
2 Recommended Board Stack-up Dimensions.............................................................................. 34
3 Trace Spacing versus Trace to Reference Plane Example ........................................................ 38
4 Two-to-One Trace Spacing-to-Trace Width Example................................................................. 38
5 Three-to-One Trace Spacing-to-Trace Width Example .............................................................. 38
6 Recommended Stack-up Capacitive Coupling Model ................................................................ 39
7 Common Clock Topology ........................................................................................................... 42
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8 Layer 6 Intel
Signals GND Referencing to Layer 5 and Layer 7 Ground Planes ............................................ 43
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9 Layer 6 Intel
Data Signals ............................................................................................................................... 44
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10 Layer 6 Intel
Source Synchronous Address Signals ....................................................................................... 45
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11 Layer 3 Intel
Signals GND Referencing to Layer 2 and Layer 4 Ground Planes ............................................ 46
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12 Layer 3 Intel
Data Signals ............................................................................................................................... 46
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13 Layer 3 Intel
Address Signals.......................................................................................................................... 47
14 Reference Trace Length Selection ............................................................................................. 57
15 Trace Length Equalization Procedures with Allegro* ................................................................. 57
16 Routing Illustration for Topology 1A ........................................................................................... 59
17 Routing Illustration for Topology 1B ........................................................................................... 60
18 Routing Illustration for Topology 1C ........................................................................................... 61
19 Routing Illustration for Topology 2A ........................................................................................... 61
20 Routing Illustration for Topology 2B ........................................................................................... 62
21 Routing Illustration for Topology 3 .............................................................................................. 63
22 Voltage Translation Circuit ......................................................................................................... 64
23 Processor RESET# Signal Routing Topology With NO ITP700FLEX Connector ...................... 64
24 Processor RESET# Signal Routing Topology With ITP700FLEX Connector ............................. 65
25 Processor RESET# Signal Routing Example with ITP700FLEX Debug Port ............................. 65
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26 Intel Pentium
(82855GME) Host Clock Layout Routing Example .................................................................... 67
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27 Intel Pentium
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28 Intel Pentium
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29 Intel Pentium
Resistive Compensation ............................................................................................................. 70
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30 Intel Pentium
Resistive Compensation ............................................................................................................. 70
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31 Intel Pentium
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32 Intel Pentium
Primary Side Layout ................................................................................................................... 71
33 COMP2 and COMP0 18-mil Wide Dog Bones and Traces ........................................................ 72
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34 Intel Pentium
35 VCCSENSE/VSSSENSE Routing Example ............................................................................... 74
36 ITP700FLEX Debug Port Signals ............................................................................................... 78
37 ITP_CLK to ITP700FLEX Connector Layout Example ............................................................... 82
38 ITP700FLEX Signals Layout Example ....................................................................................... 83
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6300ESB ICH Embedded Platform Design Guide
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Pentium M/Celeron M Processor FSB Source Synchronous
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Pentium M/Celeron M Processor FSB Source Synchronous
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Pentium M/Celeron M Processor System Bus
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Pentium M/Celeron M Processor FSB Source Synchronous
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Pentium M/Celeron M Processor FSB Source Synchronous
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Pentium M/Celeron M Processor FSB Source Synchronous
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M/Celeron M Processor and Intel
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M/Celeron M Processor GTLREF Voltage Divider Network........................... 68
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M/Celeron M Processor GTLREF Motherboard Layout ................................. 69
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M/Celeron M Processor COMP[2] and COMP[0]
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M/Celeron M ProcessorCOMP[3] and COMP[1]
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M/Celeron M Processor COMP[3:0] Resistor Layout..................................... 71
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M/Celeron M Processor COMP[1:0] Resistor Alternative
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M/Celeron M Processor Strapping Resistor Layout ....................................... 73
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855GME Chipset GMCH