Signals Gnd Referencing To Layer 5 And Layer 7 Ground Planes - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
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Intel Pentium
Source synchronous data and address signals and their associated strobes are partitioned into
groups of signals. Flight time skew minimization within the same group of source synchronous
signals is a key parameter that allows their high-frequency (400 MHz) operation. All the source
synchronous signals that belong to the same group shall be routed on the same internal layer for
the entire length of the bus. It is permissible to split different groups of source synchronous signals
between different motherboard layers as long as all the signals that belong to that group are kept on
the same layer. Grouping of the Intel Pentium M/Celeron M Processor FSB source synchronous
signals is summarized in
flight time skew because the dielectric thickness, line width, and velocity of the signals are uniform
across a single layer of the stack-up. The relationship of dielectric thickness, line width, and
velocity between layers cannot be ensured.
The source synchronous signals shall be routed as a strip-line on an internal layer with complete
reference to ground planes both above and below the signal layer. Routing with references to split
planes or power planes other than ground is not allowed. For the recommended stack-up example
as shown in Figure
routed on Layer 3 and Layer 6. Layer 2 and Layer 7 are solid grounds across the entire
motherboard. However, this is not sufficient because significant coupling exists between signal
layer, Layer 3 and power plane Layer 4 as well as signal layer, Layer 6 and power plane Layer 5.
To ensure complete ground referencing, Layer 4 and Layer 5 are converted to ground plane floods
in the areas where the source synchronous processor FSB signals are routed. In addition, all the
ground plane areas are stitched with ground vias in the vicinity of the Intel Pentium M/Celeron M
Processor and Intel 855GME chipset package outlines with the vias of the ground pins of the Intel
Pentium M/Celeron M Processor and Intel 855GME chipset pin-map.
Figure 8 illustrates a motherboard layout and a cross-sectional view of the recommended stack-up
of the Intel Pentium M/Celeron M Processor FSB source synchronous DATA and ADDRESS
signals referencing ground planes on both Layer 7 and Layer 5. In the socket cavity of the Intel
Pentium M/Celeron M Processor, Layer 5 and Layer 6 are used for VCC core power delivery.
However, outside the socket cavity Layer 6 signals are routed on top of a solid Layer 7 ground
plane and also Layer 5 is converted to a ground flood under the shadow of the Intel Pentium
M/Celeron M Processor FSB signals routing between the Intel Pentium M/Celeron M Processor
and GMCH. Stitching of all the GND planes is provided by the ground vias in the pin-map of the
Intel Pentium M/Celeron M Processor and GMCH.
Figure 8. Layer 6 Intel

Signals GND Referencing to Layer 5 and Layer 7 Ground Planes

L6 and L5 top side
view
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M/Celeron M Processor FSB Design and Power Delivery Guidelines
Table 5 and Table
2, source synchronous Intel Pentium M/Celeron M Processor FSB signals are
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Pentium M/Celeron
January 2007
6300ESB ICH Embedded Platform Design Guide
7. This practice results in a significant reduction of the
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M Processor FSB Source Synchronous
Stackup cross - section
VCC
L4
L5
L6
L7
GND
GND
VCC
FSB DATA
FSB ADDRESS
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