Debug Port Host Clock Connection; Clock Driver Decoupling And Power Delivery - Intel Pentium III Processor 512K Design Manual

4.3

Debug Port Host Clock Connection

In order to recover full front side bus speed BPM[5:0]# and RESET# data with the ITP, the Debug
Port should be placed as close as is physically reasonable to the system bus, and no further than
1.5 ns flight time (as measured by trace length of the BPM[5:0]# and RESET# signals) from the
nearest front side bus agent. System designers should record the flight time of the BPM[5:0]# and
RESET# signals from the nearest front side bus agent to the Debug Port. This value will be
important during the routing of several other Debug Port signals.
When BCLK and BCLK# (in differential clocked systems) signals are routed from the system
clock buffer to each of the synchronous clock agents with a matched length, the copy of these
signals from the system clock buffer to the ITP Debug Port must have a flight time equal to the
matched length of the other synchronous clock agents plus the flight time of the BPM[5:0]# signals
from the nearest bus agent to the Debug Port noted above. This ensures that the same BCLK to
BPM[5:0]# phase relationship seen at the closest system bus agent will be present at the Debug
Port pins. Clock trace lengths may be adjusted to center the recovery of BPM[5:0]# and RESET# at
the Debug Port within the ITP receiver setup and hold window.
For a single-ended clock driver design, the topology illustrated in Figure 15 should be used. In this
case, the "chipset" in the illustration is actually the debug port pin. The trace length L0 and the Rs
value are the same as recommendations for the chipset in Table 15. However, the length of the trace
segment L1 should be chosen so that it complies with the requirements described in the previous
paragraph. This means that the L1 for the debug port is at least as long as the L1 for the processor
clock traces.
4.4

Clock Driver Decoupling and Power Delivery

The decoupling and power delivery requirements of the system clock driver are dependent on the
clock driver and chipset used in the system implementation. Because of this, no specific
information can be provided in this document. However, since proper decoupling and noise-free
power delivery are critical to the clock driver's operation, Intel encourages system implementors to
carefully follow the chipset and clock driver vendor's recommendations in these areas. An
incorrect implementation of these circuits can easily cripple a clock driver's ability to produce
reliable clock signals and lead to system instability. Please refer to the appropriate clock driver and
chipset vendor information for more details.
Design Guide
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LV Intel Pentium III Processor 512K Dual Processor Platform
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