Ddr3 Memory Design Guidelines; Memory General Introduction; Supported Memory Configurations; Memory Population Rules - Intel Quark SoC X1000 Design Manual

DDR3 Memory Design Guidelines—Intel
3.0

DDR3 Memory Design Guidelines

3.1

Memory General Introduction

®
Intel Quark™ SoC X1000 Customer Reference Board (codename Kips Bay) platforms
support DDR3 memory technology. The CRB's SoC memory interface supports a single-
channel of DDR3 memory with 8-bit wide data and up to 2 ranks per channel at 800
MT/s.
This document covers the guidelines to design a Kips Bay platform memory subsystem
using Memory Down approach.
3.1.1

Supported Memory Configurations

Table 5.

This Guideline Supports the Following Configurations

Supports up to:
Device Densities Supported
Device Widths Supported
Memory capacity
PCB Layers
3.1.2

Memory Population Rules

Rank0 is mandatory; Rank1 is optional; All devices must be of the same bit density.
3.1.3

Reference Documents

See JEDEC Standard for DDR3 SDRAM Specification at http://jedec.org.
DDR3 TLC (Trace Length Calculator):
Clanton_DDR3_4L_single_rank_fly_by_topoology_Trace_Length_Calculator_rev_0_4_
Draft.xlsm - external version CDI# 523409
3.1.4

Design Constraints-based Routing

Design constraints need to be derived from all of the following sections:
• Memory Stackup Guidelines
• Stackup and Layer Utilization Guidelines
• Memory Block Diagram and Connectivity
• Memory Bit swapping and Byte Lane swapping
• Memory Length Matching Guidelines
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
Parameter 1 Rank/Channel 2 Ranks/Channel
DDR3-800
1Gb, 2Gb, 4Gb
x8
256MB-1GB
4L
Intel
DDR3-800
1Gb, 2Gb, 4Gb
x8
512MB-2GB
TBD
®
Quark™ SoC X1000
PDG
29