Instruction Fetches To Uncompressed; Performance; Decompression Controller Registers - IBM PowerPC 405GP User Manual

Step 2, above, indicates that compressed code is decoded "if required." Some compression blocks do
not contain compressed code, even though they reside in compressed code space. The compression
algorithm can infrequently result in blocks that are larger than the original code. In such cases, the
compression software does not compress the instruction block and marks it as uncompressed. The
decoder will not attempt to decompress such blocks.
14.1.4 Instruction Fetches to Uncompressed Pages
The decompression controller does not intercept instruction fetches to code in uncompressed
memory space. These fetches are passed, unaltered, to the appropriate memory controller. The
decompression controller also provides unaltered data, from the appropriate memory controller, back
to the CPU in the case of a read. This transaction does not incur any additional latency.
14.1.5 Performance
The decompression controller is designed so that read/write requests to uncompressed memory
spaces incur no additional latency over a system without a decompression controller.
The decompression controller adds additional latency to some read accesses to compressed
memory space. The decompression controller requires additional cycles to locate compressed code,
fetch it, decode the instructions, and place them in the output buffer. However, because instructions
are encoded in 64-byte compression blocks, the decompression controller continues to decompress
instructions until its 64-byte output buffer is full. In such cases, the decompression controller acts as a
prefetch buffer, and subsequent fetches to instructions in the same 64-byte block actually incur less
latency than if the decompression controller were not present.
More significant latencies occur when the processor core executes a branch out of the current 64-
byte block, If the branch is to a TIA that is not at the beginning of a 64-byte block, the decompression
controller must fetch and decode the block containing the TIA, byte by byte, until it reaches the
desired instruction. The worst latencies occur when the TIA is outside of the 128-byte group, since the
decompression core must then go through its entire decode process, including a refetch of the index
table entry.
14.2 Decompression Controller Registers
The registers that control operation of the decompression controller, listed in Table 14-1, are indirectly
accessed using the Decompression Controller Address Register (DCPO_CFGADDR) and
Decompression Controller Data Register (DCPO_CFGDATA) listed in Table 14-2. The
DCPO_CFGADDR and DCPO_CFGDATA are accessed using the mfdcr and mtdcr instructions.
Descriptions of the registers follow Table 14-2.
The DCPO_CFGADDR stores the address of the target register, while the DCPO_CFGDATA register
is used to write or read the target register cqntents.
The following procedure accesses the decompression controller registers.
Preliminary Decompression Controller Operation 14-3