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17.4.3 Completion Ordering
PCI bridge implements the following completion ordering rules:
1. PCI master writes are accepted if there is room in the PCI write post buffer.
2. New PCI master reads are accepted if there is no delayed read (DRR or DRC) in progress:
a. If PCI write post buffer is empty and read data is not buffered, then begin a delayed read (enter
DRR state).
b. If PCI write post buffer is not empty, then begin delayed read (enter DRR state).
Delayed reads are handled as follows:
a. While in DRR state, retry all PCI master reads. Wait for all PCI master writes if any that were
posted before entering DRR state to complete on PLB.
b. Execute PLB read, enter DRC state.
c. While in DRC state, retry all PCI master reads if the address does not match. If it does match,
pass the read data to the PCI master.
If
data is passed, exit the DRC state.
3. PLB master writes are accepted if there is room in the PLB write post buffer.
4. PLB master reads are accepted if the PLB write post buffer and the PCI write post buffer are both
empty.
17.4.3.1 PCI Producer-Consumer Model
The PCI Producer-Consumer model is followed with one exception: PCI master reads do not flush
PLB writes and PCI master writes do not cause PLB prefetched read data to be discarded. If the "flag"
is stored in system memory (PLB side), but the "data" is stored in a PCI target, the control software
must manually force coherency. This can be done by following two rules:
1 . To ensure data written by a PLB master has reached the intended PCI target, the PLB master
should execute a read from PCI, to any nondestructive address. This is only necessary if the write
is postable.
2. To ensure data read by a PLB master is current (rather than old prefetched data), the PLB master
should execute a read from PCI to any other nondestructive address. This is only necessary if the
read is prefetchable.
17.4.4 Collision Resolution
The PCI bridge must resolve collisions when a PLB master and a PCI master attempt accesses
through the PCI bridge at the same time. Table 17-7 summarizes collision resolution.
In general, PLB postable writes are always accepted (if buffer space is available), and passed to the
PCI when given the chance. PCI master writes are always accepted (if buffer space is available), but
cause PLB reads and non-postable writes to be rearbitrated to clear the path to the PLB. PLB reads
and non-postable writes proceed as long as there is no PCI master acti.vity, which causes the PLB
cycle to be rearbitrated. PCI master reads are always allowed to proceed, and cause PLB reads and
non-postable writes to be rearbitrated.
Internal configuration accesses have their own rules. Configuration writes are not allowed to complete
while any write data is posted in the PCI bridge, or while the PCI master is prefetching. Otherwise,
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PPC405GP User's Manual
Preliminary
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