Powerpc Processor Core Features - IBM PowerPC 405GP User Manual

• External bus controller (EBC)
- Flash ROM/Boot ROM interface
- Direct support for 8-,16-, or 32-bit SRAM or external peripherals
- One external master supported
• PCI bus, Revision 2.2 compliant (32 bit, up to 66 MHz)
- PCI bus interface can be configured to operate synchronously or asynchronously to the PLB
- Internal PCI bus arbiter that can be disabled for use with an external arbiter
• DMA support for OPB and external peripherals
• Ethernet 10/100 Mbps (full-duplex) controller with media access layer (MAL) support
• Interrupt controller supporting programmable interrupt handling from a variety of sources
• Two 8-bit serial ports (16550 compatible UARTs)
• Inter-integrated circuit (IIC) controller
• General purpose I/O (GPIO) controller
1.1.2 PowerPC Processor Core Features
The PowerPC RISC fixed-point CPU features:
• PowerPC User Instruction Set Architecture (UISA) and extensions for embedded applications
• Thirty-two 32-bit general purpose registers (GPRs)
• Static branch prediction
• Five-stage pipeline with single-cycle execution of most instructions, including loads/stores
• Unaligned load/store support to cache arrays, main memory, and on-Chip memory (OCM)
• Hardware multiply/divide for faster integer arithmetic (4-cycle multiply, 35-cycle divide)
• Multiply-accumulate instructions
• Enhanced string and multiple-word handling
• True little end ian operation
• Programmable Interval Timer (PIT), Fixed Interval Timer (FIT), and watchdog timer
• Forward and reverse trace from a trigger event
• Storage control
- Separate, configurable, two-way set-associative instruction and data cache units
- Eight words (32 bytes) per cache line
- 16KB instruction and 8KB data cache arrays
- Instruction cache unit (ICU) non-blocking during line fills, data cache unit (DCU) non-blocking
during line fills and flushes
- Read and write line buffers
- Instruction fetch hits are supplied from line buffer
- Data load/store hits are supplied to line buffer
- Programmable ICU prefetching of next sequential line into line buffer
Preliminary Overview 1-3