System Reset; Pci Power Management Initiated Resets; Processor Initiated Resets; Processor State After Reset - IBM PowerPC 405GP User Manual

During chip reset, the ExtReset signal is driven low to ensure the reset of synchronous devices that
use the external bus clock signal, PerClk.
8.2.3 System Reset
A system reset results in a reset of all PPC405GP logic, including the processor core, internal phase-
locked loop (PLL), and on-chip peripherals. A system reset can be initiated externally or internally.
External system resets are initiated by the assertion of the SysReset signal for at least 16 SysClk
cycles. Internal system resets are initiated by either the processor core or PCI power management
logic.
When a system reset is requested internally, the bidirectional open drain SysReset signal is asserted
to enable other chips to be reset at the same time. In this case, the SysReset signal is driven low for
8192 SysClk cycles, resulting in a System reset of the PPC405GP chip and all other devices attached
to the reset network connected to SysReset.
After the SysReset signal is deasserted, the PLL begins its locking process, which also requires 8192
SysClk cycles. When 64 SysClk cycles remain, the internal PPC405GP clocks (OPS, PCI, EXT, and
Serial) begin toggling. The PLS and CPU clocks toggle while SysReset is asserted, and during the
PLL locking process. When the PLL lock timer expires, internal resets are released, and the
processor core begins its initial instruction fetch.
During system reset, the ExtReset signal is driven low to ensure the reset of synchronous devices
that use the external bus clock signal, PerClk.
8.3 pel Power Management Initiated Resets
An external PCI master can write the Power Management Control/Status Register (PCICO_PMCSR)
to request a change from the D3hot PCI power management state to the DO state. The on-chip PCI
logic always accepts such a write and assumes that requested state changes from D3hot are always
to DO. After receiving such a write, the PCI logic asserts a signal that immediately results in an
internally requested system reset.
8.4 Processor Initiated Resets
The processor core in the PPC405GP can request three types of processor resets: core, chip, and
system. Each type of reset can be generated by a JTAG debug tool, by the second expiration of the
watchdog timer, or by writing a non-zero value to the Reset (RST) field of the Debug Control Register
o
(DBCRO).
The effects of core and chip resets on the processor core are identical. To determine which reset type
occurred, the most-recent reset (MRR) field of the Debug Status Register (DSSR) can be examined.
8.5 Processor State After Reset
After a reset, the contents of the Machine State Register (MSR) and the Special Purpose Registers
(SPRs) control the initial processor state. The contents of Device Control Registers (DCRs) control
the initial states' of on-chip devices. Chapter 25, "Register Summary," contains descriptions of the
registers.
8-2 PPC405GP User's Manual Preliminary