IBM PowerPC 405GP User Manual page 612

Using sleep mode dynamically requires careful software control to make sure the UARTs are idle
before putting them to sleep.
21.6 DMA Operation
The DMA controller can be configured to perform DMA operations using UARTO, which appears as an
8-bit peripheral to the DMA controller. When selected, the UART receiver is internally wired to the
DMAReq and DMAAck signals of DMA channel 2, and the transmitter is internally wired to the
DMAReq and DMAAck signals of DMA channel 3.
The UART can be operated in FIFO mode or non-FIFO mode. In FIFO mode, the transfers can be
done as single transfers (DMA mode 0) or multiple transfers (DMA mode 1), depending on the setting
of the OMS field in the FIFO Control Register (FCR). In non-FIFO mode, DMA transfers are
performed using single transfers, using the UART's DMA mode O. This section describes proper
UARTO DMA programming. For more information on general DMA programming, see Chapter 18,
"Direct Memory Access Controller:' on page 18-1.
21.6.1 Chip Control Register 0 (CPCO_CRO)
Only CPCO_CRO fields related to UART are shown in Figure 21-13. Other non-related functions are
not shown here.
DCS DTE DAEC U1EC
10
+ + + +
30 1311
t t t
t
RDS ORE UOEC UDIV
Figure 21-13. Chip Control Register 0 (CPCO_CRO)
0:18 Reserved.
19 DCS DSRlCTS select
o
DSR is selected.
1 CTS is selected.
20
RDS RTS/DTR select
o
RTS is selected.
1 DTR is selected.
21 DTE DMA Transmit Enable for UARTO
o
DMA transmit channel is disabled.
1 DMA transmit channel is enabled.
22 DRE DMA Receive Enable for UARTO
o
DMA receive channel is disabled.
1 DMA receive channel is enabled.
Preliminary
Serial Port Operations 21-17