IBM PowerPC 405GP User Manual page 37

Figure 25-16. Data Cache Cachability Register (DCCR) ........................................................................... 25-38
Figure 25-17. Decompression Address Decode Definition Registers (DCPO_ADDRO-DCPO_ADDR1) ... 25-40
Figure 25-18. Decompression Controller Configuration Register (DCPO_CFG) ........................................ 25-41
Figure 25-19. Decompression Controller Error Status Register
°
(DCPO_ESR) ........................................ 25-44
Figure 25-20. Decompression Controller
10
Register (DCPO_ID) .............................................................. 25-46
Figure 25-21. Decompression Index Table Origin Registers (DCPO_ITORO-DCPO_ITOR3) .................... 25-47
Figure 25-22. Decompression Controller Bus Error Address Register (DCPO_MEMBEAR) ...................... 25-48
Figure 25-23. Decompression Controller PLB Error Address Register (DCPO_PLBBEAR) ....................... 25-49
Figure 25-24. Decompression Controller Version Register (DCPO_ VER) ...............................
1 . . . . . . . . . . . . . . . . . .
25-51
Figure 25-25. Data Cache Write-through Register (DCWR) ...................................................................... 25-52
Figure 25-26. Data Exception Address Register (DEAR) ........................................................................... 25-54
Figure 25-27. DMA Channel Control Registers (DMAO_CRO-DMAO_CR3) ............................................... 25-55
Figure 25-28. DMA Count Registers (DMAO_CTO-DMAO_CT3) ................................................................ 25-58
Figure 25-29. DMA Destination Address Registers (DMAO_DAO-DMAO_DA3) ......................................... 25-59
Figure 25-30. DMA Polarity Configuration Register (DMAO_POL) ............................................................. 25-60
Figure 25-31. DMA Source Address Registers (DMAO_SAO-DMAO_SA3) ............................................... 25-62
Figure 25-32. DMA Scatter/Gather Descriptor Address Registers (DMAO_SGO-DMAO_SG3) ................. 25-63
Figure 25-33. DMA Scatter/Gather Command Register (DMAO_SGC) ...................................................... 25-64
Figure 25-34. DMA Sleep Mode Register (DMAO_SLP) ............................................................................ 25-65
Figure 25-35. DMA Status Register (DMAO_SR) ....................................................................................... 25-66
Figure 25-36. Data Value Compare Registers (DVC1-DVC2) ................................................................... 25-67
Figure 25-37. Peripheral Bus Error Address Register (EBCO_BEAR) ....................................................... 25-68
Figure 25-38. Peripheral Bus Error Status Register
°
(EBCO_BESRO) ..................................................... 25-69
Figure 25-39. Peripheral Bus Error Status Register 1 (EBCO_BESR1) ..................................................... 25-71
Figure 25-40. Peripheral Bank Access Parameters (EBCO_BnAP) ........................................................... 25-73
Figure 25-41. Peripheral Bank Configuration Registers (EBCO_BnCR) ..................................................... 25-75
Figure 25-42. EBC Configuration Register (EBCO_CFG) ........................................................................... 25-76
Figure 25-43. Group Address Hash Tables 1-4 (EMACO_GAHT1-EMACO_GAHT4) ............................... 25-80
Figure 25-44. Individual Address High Register (EMACO_IAHR) ............................................................... 25-81
Figure 25-45. STA Control Register (EMACO_STACR) ............................................................................. 25-82
Figure 25-46. Transmit Mode Register
°
(EMACO_ TMRO) ........................................................................ 25-83
Figure 25-47. Transmit Mode Register 1 (EMACO_ TMR1) ........................................................................ 25-84
Figure 25-48. Transmit Request Threshold Register (EMACO_ TRTR) ...................................................... 25-85
Figure 25-49. VLAN TCI Register (EMACO_ VTCI) ..................................................................................... 25-86
Figure 25-50. VLAN TPID Register (EMACO_ VTPID) ................................................................................ 25-87
Figure 25-51. Exception Syndrome Register (ESR) ................................................................................... 25-88
Figure 25-52. Exception Vector Prefix Register (EVPR) ............................................................................ 25-89
Figure 25-53. GPIO Input Register (GPIOO_IR) ......................................................................................... 25-90
Figure 25-54. GPIO Open Drain Register (GPIOO_ODR) .......................................................................... 25-91
Figure 25-55. GPIO Output Register (GPIOO_OR) .................................................................................... 25-92
Figure 25-56. GPIO Three-State Register (GPIOO_ TCR) .......................................................................... 25-93
Figure 25-57. General Purpose Registers (RO-R31) .................................................................................. 25-94
Figure 25-58. Instruction Address Compare Registers (IAC1-IAC4) ................................................... , ..... 25-95
Figure 25-59. Instruction Cache Cachability Register (ICCR) .................................................................... 25-96
Figure 25-60. Instruction Cache Debug Data Register (ICDBDR) ............................................................. 25-98
Figure 25-61. IICO Clock Divide Register (IICO_CLKDIV) .......................................................................... 25-99
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PPC405GP User's Manual Preliminary