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settings for UARTO transmit transfers. Other DMA registers and register fields must be programmed
appropriately, see Chapter 18, "Direct Memory Access Controller:' on page 18-1 for more information.
Table
21·5.
UARTO Transmitter DMA Mode Register Field Settings
Register [Field]
Meaning
CPCO_CRO[DTE]=1
UARTO DMA Transmit channel is enabled using DMA channel 3.
CPCO_CRO[DAEC]
Set to 0 to not clear CPCO_CRO[DTE] enable when terminal count is
reached, set to 1 to clear enable when terminal count is reached.
DMAO_CR3[TD]=O
DMA Channel 3 transfer direction is from memory to peripheral.
DMAO_CR3[PL]=1
DMA Channel 3 peripheral is on the OPB (UARTO).
DMAO_CR3[PW]=OO
Peripheral width is byte (8 bits).
DMAO_CR3[TM]=OO
DMA Channel 3 is in peripheral mode.
DMAO_CR3[PWC]=OOOO10
Peripheral Wait cycles, how long the internal DMAck is active. Three
cycles are required.
DMAO_CR3[PHC]=OOO
Peripheral Hold Cycles are O.
DMAO_CR3[ETD]=1
EOTfTC is programmed as terminal count output.
UARTO_FCR[DMS]
Set to 0 for a single DMA transfer or 1 for multiple DMA transfers.
Note: When using DMA Channel 3 for UARTO transmitter transfers, external DMA transfers cannot
be performed on this channel.
Preliminary
Serial Port Operations
21·19
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