IBM PowerPC 405GP User Manual page 569

The buffer descriptor table forms a circular queue with a programmable length. The last descriptor in
the table is defined by setting the Wrap bit in the status/control field (see "Status/Control Field
Format" on page 20-14). If there is no Wrap bit set in the table, then MAL automatically wraps after
processing 256 descriptors (the maximum number of descriptors allow per channel).
The format of the buffer descriptor (see Figure 20-5) is the same for all COMMACs, and has the same
structure for both transmit and receive. The most significant halfword in each buffer descriptor
contains a status/control halfword. This field contains two parts: the first part (6 bits) is SD handling
information used by the MAL for descriptor processing, the second field (10 bits) is content specific for
each COMMAC. The second halfword determines the data length referenced in this buffer descriptor.
The second word in the buffer descriptor contains a 32 bit data buffer pointer that pOints to the actual
data buffer in memory. It is suggested that each data buffer start on a cache line boundary and be a
multiple of a cache line in size if it resides in cachable memory. (The cache line size in the PPC405
processor core is 32 bytes.)
o
15 16 20 31
Offset
+
0
Status/Control
I
Not in Use
I
Data Length
Offset
+
4
Data Buffer Pointer
Figure 20-5. Buffer Descriptor Structure
A packet may reside in as many buffers as necessary (transmit or receive). Each buffer has a
maximum length of (4KS - 16) bytes. In TX channels, the buffer descriptor length field is written by the
device driver and defines the number of bytes in the data buffer that is identified by the data buffer
pointer. In RX channels, the buffer descriptor length field is written by MAL and defines the number of
bytes written by MAL to the buffer that is identified by the data buffer pointer (see "Receive Software
Interface" on page 20-12).
When processing a packet, MAL does not assume that all buffers of the current packet are already
valid. It expects the buffers to be ready in due time to be transmitted or received. Failure of the
software to provide the descriptors in due time may result in .an error.
20-8 PPC405GP User's Manual Preliminary