IBM PowerPC 405GP User Manual page 46

Table 24-32. Extended Mnemonics for tlbre .............................................................................................. 24-185
Table 24-33. Extended Mnemonics for tlbwe ............................................................................................. 24-189
Table 24-34. Extended Mnemonics for tw ................................................................................................. 24-191
Table 24-35. Extended Mnemonics for twi ................................................................................................. 24-194
Table 25-1. PPC405GP General Purpose Registers ...................................................................................... 25-1
Table 25-2. Special Purpose Registers ......................................................................................................... 25-2
Table 25-3. Time Base Registers ................................................................................................................... 25-4
Table 25-4. Directly Accessed DCRs ............................................................................................................. 25-4
Table 25-5. SDRAM Controller DCR
Usag~
.................................................................................................. 25-7
Table 25-6. Offsets for SDRAM Controller Registers .................................................................................... 25-7
Table 25-7. EBC DCR Usage ........................................................................................................................ 25-8
Table 25-8. Offsets for EBC Registers ........................................................................................................... 25-8
Table 25-9. Decompression Controller DCR Usage ...................................................................................... 25-9
Table 25-10. Offsets for Decompression Controller Registers ...................................................................... 25-9
Table 25-11. Directly Accessed MMIO Registers ........................................................................................ 25-10
Table 25-12. PCI Configuration Address and Data Registers ...................................................... : .............. 25-13
Table 25-13. PCI Configuration Registers .................................................................................................. 25-13
Table 26-1. Alphabetical Signal List. ............................................................................................................... 26-1
Table 26-2. Signal Descriptions .................................................................. : .................................................. 26-5
Table A-1. PPC405GP Instruction Syntax Summary ...................................................................................... A-1
Table A-2. PPC405GP Instructions by Opcode ............................................................................................ A-33
Table B-1. PPC405GP Instruction Set Functional Summary .......................................................................... B-1
Table B-2. Implementation-specific Instructions ............................................................................................. B-1
Table B-3. Instructions in the IBM PowerPC Embedded Environment ........................................................... B-5
Table B-4. Privileged Instructions ....................................................................................................... : ........... B-7
Table B-5. Extended Mnemonics for PPC405GP ......................................................................................... B-10
Table B-6. Storage Reference Instructions ................................................................................................... B-29
Table B-7. Arithmetic and Logical Instructions .............................................................................................. B-33
Table B-8. Condition Register Logical Instructions ....................................................................................... B-37
Table B-9. Branch Instructions .................................... ~ ................................................................................. B-38
Table B-10. Comparison Instructions ........................................................................... : ................................ B-39
Table B-11. Rotate and Shift Instructions ............................................................................................
~
........ B-40
Table B-12. Cache Control Instructions ........................................................................................................ B-41
Table B-13. Interrupt Control Instructions ....................................................................................... : ............. B-42
Table B-14. Processor Management Instructions ......................................................................................... B-42
Table C-1. Cache Sizes, Tag Fields, and Lines .............................................................................................. C-2
Table C-2. Multiply and MAC Instruction Timing ............................................................................................. C-5
Table C-4. Instruction Cache Miss Penalties .................................................................................................. C-7
Preliminary Tables
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