IBM PowerPC 405GP User Manual page 409

BA PF LT
*
12\11
* *
t
f
BAZ
MSI
Figure 17-35. PCI PTM 1 BAR Register (PCICO_PTM1 BAR)
31:12 BA Base Address Only corresponding bits in PCILO_PTM1 MS
These bits determine where in PCI memory
that are set to 1 are writable. Bits in
address space this region is located. PCILO_PTM1 MS that are set to 0 cause
the corresponding Base Address register
bits to be always O. PCILO_PTM1 MS must
be initialized by a PLB master before any
PCI device is allowed to configure this
register.
11:4 BAZ Base Address Always Zero BAZ
=
OxOO because the minimum size of
this range is 4KB.
3 PF Prefetchable PR
=
1 to indicate that prefetching is
allowed.
2:1
LT
Location Type
LT
=
ObOO to indicate that the memory
space can be located anywhere in the 32-
bit address space.
0
MSI Memory Space Indicator MSI
=
0 to indicate memory space, rather
than I/O space.
17.5.3.15 PCI PTM 2 BAR (PCICO_PTM2BAR)
PCICO_PTM2BAR defines a second space in PCI memory space that is mapped to PLB space
(system memory or ROM). Note that if PCICO_PTM2BAR is disabled using PCILO_PTM2MSA,
PCICO_PTM2BAR cannot be written. Set PCICO_PTM2BAR to
°
before disabling this bit. If disabled
in this way, reads to PCICO_PTM2BAR always return 0.
17-38
PPC405GP User's Manual
Preliminary