Uic Vector Register (Uico_Vr) - IBM PowerPC 405GP User Manual

The bit closest to the highest priority field that is programmed in the UICO_CR as a interrupt has the
second highest priority. Priority decreases across the UICO_SR to the end opposite the highest
priority field.
VBA
10
*
29 13013 1
1
t
PRO
Figure 10-7. UIC Vector Configuration Register (UICO_ VCR)
0:29 VBA Vector Base Address
30 Reserved
31
PRO Priority Ordering
o
UICO_SR[O] is the highest priority
interrupt.
1 UICO_SR[31] is the highest priority
interrupt.
Note: Vector generation is not performed
for non-critical interrupts.
10.5.8 UIC Vector Register (UICO_ VR)
The read-only UICO_ VR contains an interrupt vector that can reduce interrupt handling latency for
critical interrupts. Vector generation logic adds an offset to UICO_ VCR[VBA], and the sum is returned
in the UICO_ VR. Vectors are not computed for non-critical interrupts.
The interrupt vector is based on the field position of the current highest priority, enabled, active,
critical interrupt relative to the highest priority interrupt in the UICO_SR. The generated vectors can be
programmed to point directly to the interrupt handlers. .
Programming Note: Regardless of the programming of UICO_ VCR and UICO_ VR registers, the
processor always vectors to EVPR[O:16] II Ox100 when a critical interrupt occurs.
The interrupt vector offset is based on the bit position of the current highest priority, enabled, active,
critical interrupt relative to the highest priority interrupt in the UICO_SR. The offset has a fixed value of
512 per bit. The main critical interrupt handler can interpret the vector returned by U ICO_ VR as the
address of the interrupt handler for that interrupt, assuming the routine is 512 bytes or smaller.
Alternatively, the main critical interrupt handler can interpret the vector as a look-up table entry for the
address of the interrupt handler for that interrupt.
Preliminary Interrupt Controller Operations 10-19