IBM PowerPC 405GP User Manual page 32

Figure 15-1. SDRAM Controller Signals ....................................................................................................... 15-1
Figure 15-2. Memory Controller Configuration (SDRAMO_CFG) .................................................................. 15-4
Figure 15-3. Memory Controller Status (SDRAMO_STATUS) ...................................................................... 15-5
Figure 15-4. Memory Bank 0-3 Configuration Registers (SDRAMO_BOCR-SDRAMO_B3CR) ................... 15-6
Figure 15-5. SDRAM Timing Register (SDRAMO_ TR) ................................................................................. 15-9
Figure 15-6. Activate, Four Word Read, Precharge, Activate ..................................................................... 15-11
Figure 15-7. Activate, Four Word Write, Precharge, Activate ..................................................................... 15-11
Figure 15-8. Precharge All, Activate ........................................................................................................... 15-12
Figure 15-9. CAS Before RAS Refresh ....................................................................................................... 15-12
Figure 15-11. Refresh Timing Register (SDRAMO_RTR) ........................................................................... 15-14
Figure 15-12. ECC Configuration Register (SDRAMO_ECCCFG) .............................................................. 15-,15
Figure 15-13. ECC Error Status Register (SDRAMO_ECCESR) ................................................................ 15-16
Figure 15-14. Bus Error Address Register (SDRAMO_BEAR) .................................................................... 15-17
Figure 15-15. Bus Error Syndrome Register 0 (SDRAMO_BESRO) ........................................................... 15-17
Figure 15-16. Bus Error Status Register 1 (SDRAMO_BESR1) .................................................................. 15-19
Figure 15-17. Power Management Idle Timer (SDRAMO_PMIT) ............................................................... 15-20
Figure 16-1. External Bus Controller Signals ................................................................................................ 16-2
Figure 16-2. Attachment of Devices of Various Widths to the Peripheral Data Bus ..................................... 16-4
Figure 16-3. Single Read Transfer ................................................................................................................ 16-6
Figure 16-4. Single Write Transfer ................................................................................................................ 16-7
Figure 16-5. Burst Read Transfer ................................................................................................................. 16-9
Figure 16-6. Burst Write Transfer ............................................................................................................... 16-10
Figure 16-7. Device-Paced Single Read Transfer ...................................................................................... 16-12
Figure 16-8. Device-Paced Single Write Transfer ...................................................................................... 16-13
Figure 16-9. Device-Paced Burst Read Transfer ........................................................................................ 16-14
Figure 16-10. Device-Paced Burst Write Transfer ...................................................................................... 16-16
Figure 16-11. Sample External Bus Master System ................................................................................... 16-17
Figure 16-12. External Master Arbitration, Single Read and Single Write .................................................. 16-20
Figure 16-13. External Master Burst Read ................................................................................................. 16-21
Figure 16-14. External Master Burst Write .................................................................................................. 16-22
Figure 16-15. EBC Configuration Register (EBCO_CFG) ........................................................................... 16-24
Figure 16-16. Peripheral Bank Configuration Registers (EBCO_BnCR) ..................................................... 16-25
Figure 16-17. Peripheral Bank Access Parameters (EBCO_BnAP) ............................................................ 16-26
Figure 16-18. Peripheral Bus Error Address Register (EBCO_BEAR) ........................................................ 16-30
Figure 16-19. Peripheral Bus Error Status Register 0 (EBCO_BESRO) ...................................................... 16-30
Figure 16-20. Peripheral Bus Error Status Register 1 (EBCO_BESR1) ...................................................... 16-32
Figure 17-1. PCI Bridge Block Diagram ........................................................................................................ 17-2
Figure 17-2. PLB-to-PCI Half-Bridge Block Diagram .................................................................................... 17-4
Figure 17-3. PCI-to-PLB Half-Bridge Block Diagram .................................................................................... 17-5
Figure 17-4. Arbitration Structure .................................................................................................................. 17-5
Figure 17-5. PMM Register Sets Map PLB Address Space to PCI Address Space ..................................... 17-8
Figure 17-6. PTM Register Sets Map PCI Address Space to PLB Address Space ...................................... 17-9
Figure 17-7. PMM 0 Local Address Register (PCILO_PMMOLA) ................................................................ 17-21
Figure 17-8. PMM 0 Mask/Attribute Register (PCILO_PMMOMA) ............................................................... 17-22
Figure 17-9. PMM 0 PCI Low Address Register (PCILO_PMMOPCILA) ..................................................... 17-23
Figure 17-10. PMM 0 High Address Register (PCILO_PMMOPCIHA) ........................................................ 17-23
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