Interrupt Handling Priorities - IBM PowerPC 405GP User Manual

interrupt save/restore register contains the address of the instruction being fetched when the machine
check occurred.
The synchronism of instruction-side machine checks (errors that occur while attempting to fetch an
instruction from external memory) requires further explanation. Fetch requests to cachable memory
that miss in the instruction cache unit (ICU) cause an instruction cache line fill (eight words). If any
instructions (words) in the fetched line are associated with an exception, an interrupt occurs upon
attempted execution and the cache line is invalidated.
It is improper to declare an exception when an erroneous word is passed to the fetcher; the address
could be the result of an incorrect speculative access. It is quite likely that no attempt will be made to
execute an instruction from the erroneous address. An instruction-side machine check interrupt
occurs only when execution is attempted. If an exception occurs, execution is suppressed, SRR2
contains the erroneous address, and the ESR indicates that an instruction-side machine check
occurred. Although such an interrupt is clearly asynchronous to the erroneous memory access, it is
handled synchronously with respect to the attempted execution from the erroneous address.
Except for machine checks, all PPC405GP interrupts are handled precisely:
• The address of the excepting instruction (for synchronous exceptions, other than the system call
exception) or the address of the next sequential instruction (for asynchronous exceptions and the
system call exception) is passed to the interrupt handling routine.
• All instructions that precede the instruction whose address is reported to the interrupt handling
routine have completed execution and that no subsequent instruction has begun execution. The
specific instruction whose address is reported might not have begun execution or might have
partially completed, as specified for each interrupt type.
10.9 Interrupt Handling Priorities
The PPC405GP processor core handles only one interrupt at a time. Multiple simultaneous interrupts
are handled in the priority order shown in Table 10-3 (assuming, of course, that the interrupt types are
enabled).
Multiple interrupts can exist simultaneously, each of which requires the generation of an interrupt. The
architecture does not provide for simultaneously reporting more than one interrupt of the same class
(critical or non-critical). Therefore, interrupts are ordered with respect to each other. A masking
mechanism is available for certain persistent interrupt types.
When an interrupt type is masked, and an event causes an exception which would normally generate
an interrupt of that type, the exception persists as a status bit in a register. However, no interrupt is
generated. Later, if the interrupt type is enabled (unmasked), and the exception status has not been
cleared by software, the interrupt due to the original exception event is finally generated.
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