IBM PowerPC 405GP User Manual page 378

Table 17-3. PLB Address Map (continued)
PLB Address PCI Address
Range
Description Range
OxEF400000- PCI Bridge Local Configuration Registers
OxEF4FFFFF
OxEF400000: PCILO_PMMOLA
OxEF400004: PCILO_PMMOMA
OxEF400008: PCILO_PMMOPCILA
OxEF40000C: PCILO_PMMOPCIHA
OxEF400010: PCILO_PMM1LA
OxEF400014: PCILO_PMM1 MA
OxEF400018: PCILO_PMM1 PCILA
OxEF40001 C: PCILO_PMM 1 PCIHA
OxEF400020: PCILO_PMM2LA
OxEF400024: PCILO_PMM2MA
OxEF400028: PCILO_PMM2PCILA
OxEF40002C: PCILO_PMM2PCIHA
OxEF400030: PCILO_PTM1 MS
OxEF400034: PCILO_PTM1 LA
OxEF400038: PCILO_PTM2MS
OxEF40003C: PCILO_PTM2LA
OxF400040-OxEF4FFFFF: Reserved (can mirror PCllocal
registers)
OxOOOOOOOO- PCI Memory-Range 0 OxOOOOOOOOOOOOOOOO-
OxFFFF FFFF
il
*
PMM 0 registers map a region in PLB space to a region in PCI OxFFFFFFFFFFFFFFFF
memory space. The address ranges are fully programmable.
The PCI address is 64 bits.
OxOOOOOOOO-
PCI Memory-Range 1 OxOOOOOOOOOOOOOOOO-
OxFFFF FFFF*
PMM 1 registers map a region in PLB space to a region in PCI OxFFFFFFFFFFFFFFFF
memory space. The address ranges are fully programmable.
The PCI address is 64 bits.
OxOOOOOOOO- PCI Memory-Range 2 OxOOOOOOOOOOOOOOOO-
OxFFFF FFFF*
PMM 2 registers map a region in PLB space to a region in PCI OxFFFFFFFFFFFFFFFF
memory space. The address ranges are fully programmable.
The PCI address is 64 bits.
* Memory map ranges are fully programmable. The ranges must not overlap with each other or conflict with any
other memory mappings.
Three PCI bridge address ranges, associated with PLB masters in PLB space, are mapped to PCI
memory space: PCI master map (PMM) 0, PMM1, and PMM2.
Each PMM is configured using the following registers (n is 0, 1, or 2, corresponding with PMMO,
PMM1, and PMM2, respectively):
• PMMnLocal Address (PCILO_PMMnLA)
• PMMnMasklAttribute (PCILO_PMMnMA)
• PMMnPCI Low Address (PCILO_PMMnPCILA)
• PMMnPCI High Address (PCILO_PMMnPCIHA)
The location of each PMM in PLB space is programmable, using the PCILO_PMMnLA registers. The
PLB address range assigned to each PMM should not overlap any other PLB address space range
that is used or reserved. Overlapping results in undefined behavior.
Preliminary
PCI Interface
17-7