Mmio Register Contents After Reset; Table 8-4. Mmio Register Contents After Reset - IBM PowerPC 405GP User Manual

Table 8·3. DCR Contents After Reset (continued)
Register Bits Reset Value Comment
SDRAMO_BEAR 0:31 OxOOOOOOOO
SDRAMO_BESRO 0:31 OxOOOOOOOO
SDRAMO_BESR1 0:31 OxOOOOOOOO
SDRAMO_CFG 0:31 OxOOOOOOOO
SDRAMO_ECCCFG
0:31 OxOOOOOOOO
SDRAMO_ECCESR
0:31 OxOOOOOOOO
SDRAMO_PMIT
0:31 Ox07COOOOO
SDRAMO.,..:RTR
0:31 Ox05FOOOOO
SDRAMO_TR 0:31 Ox00854009
Universal Interrupt Controller (UIC)
UICO_CR Undefined
UICO_ER OxOOOOOOOO
UICO_MSR Undefined
UICO_PR Undefined
UICO_SR Undefined
UICO_TR Undefined
UICO_VCR Undefined
UICO_VR Undefined
8.8 MMIO Register Contents After Reset
MMIO registers are unaffected by core resets, and are generally identical for chip and system resets.
Table 8·4. MMIO Register Contents After Reset
Register Bits Reset Value
Comment
Ethernet (EMAC)
EMACO_GAHT1 0:31 OxOOOOOOOO
EMACO_GAHT2 0:31 OxOOOOOOOO
EMACO_GAHT3 0:31 OxOOOOOOOO
EMACO_GAHT4 0:31
OxOOOOOOOO
EMACO_IAHR 0:31 OxOOOOOOOO
EMACO_IAHT1 0:31 OxOOOOOOOO
EMACO_IAHT2 0:31 OxOOOOOOOO
EMACO_IAHT3 0:31 OxOOOOOOOO
8·8 PPC405GP User's Manual Preliminary