IBM PowerPC 405GP User Manual page 556

TRT
1
0
*
3 1
1
Figure 19-33. Transmit Request Threshold Register (EMACO_ TRTR)
0:4
TRT
Transmit Request Threshold
The following number of bytes must be
placed in the Transmit FIFO before
initiating a transmit request.
00000 64 bytes
00001 128 bytes
00010 192 bytes
00011 256 bytes
11111 2048 bytes
5:31 Reserved
19.7.20 Receive Low/High Water Mark Register (EMACO_RWMR)
The EMACO_RWMR defines the conditions that cause EMAC to activate a low or urgent priority MAL
request, and that manage flow control.
EMAC activates a low priority request if the number of occupied entries in the Receive FIFO is greater
than or equal to the content of EMACO_RWMR[RLWM] (the receive low water mark is reached). A
request for a pause packet with a pause_value of (j is also issued when the receive low water mark is
reached.
Software must coordinate the value of EMACO_RWMR[RLWM] with the value of EMACO_MR1 [RFS].
EMACO_RWMR[RLWM] should be smaller than EMACO_MR1 [RFS] and larger than the MAL burst
length.
Note: In the 405GP, the MAL burst length is 16 words for all channels.
If the entire packet is already in the Receive FIFO, EMAC initiates a low priority request regardless of
the programmed value.
EMAC activates an urgent priority request if the number of occupied entries in the Receive FIFO is
greater than or equal to EMACO_RWMR[RHWM] (the receive high water mark is reached). A request
for a pause packet is also issued when the receive high water mark is reached.
Software must coordinate the value of EMACO_RWMR[RHWM] with the value of EMACO_MR1 [RFS].
EMACO_RWMR[RHWM] should be greater than the value of EMACO_RWMR[RLWM] and less then
the size of the Receive FIFO.
Preliminary Ethernet Media Access Controller 19-41