IBM PowerPC 405GP User Manual page 578

20.6.6.2 Bit 1 - W - Wrap
o -
This is not the last data buffer descriptor in the buffer descriptor table.
1 - This is the last data buffer descriptor in the buffer descriptor table. After this buffer has been used,
MAL will transfer data to the first buffer descriptor in the table.
This bit is controlled by software only. It controls MAL activities and does not affect the COMMAC
channel.
20.6.6.3 Bit 2 - CM - Continuous Mode
o -
Normal Operation
1 - Continuous Operation. After this buffer descriptor is closed, the E-bit is not cleared by MAl. This
ensures that the data buffer is ready to receive data when MAL next accesses its buffer descriptor.
However, the E-bit is cleared if an error occurs during reception.
This bit is controlled by software only. It controls MAL activities and does not affect the COMMAC
channel.
20.6.6.4 Bit 3 - L - Last
0-
This is not the last buffer in the current packet.
1 - This is the last buffer in the current packet.
This bit is updated by MAL following the activity of the channel.
20.6.6.5 Bit 4 - F - First
0- This is not the first buffer in the current packet.
1 - This is the first buffer in the current packet.
This bit is updated by MAL following the activity of the channel.
20.6.6.6 Bit 5 - I - Interrupt
1 - After finish processing the current buffer, if this bit is 1, the end of buffer field in the End of Buffer
Interrupt Status Register is set and the end of buffer interrupt is asserted.
o -
No action is taken by MAL at the end of the current buffer.
MAL asserts the end of buffer interrupt after updating the buffer descriptor's status field.
This bit is controlled by software only. It controls MAL activities and does not affect the COMMAC.
20.6.6.7 Bits 6 to 15
These bits are COM MAC-specific and they may contain control fields generated by the software in
order to control the COM MAC channel. They may also contain status fields generated by the
COMMAC channel to be processed by software.
Preliminary Memory Access Layer 20-17