Debug Modes; Internal Debug Mode; External Debug Mode - IBM PowerPC 405GP User Manual

Table 12-3. RISCTrace Header Pin Description (continued)
Pin Signal Name Pin Signal Name
10 No connect 20 GND
12.6 Debug Modes
The PPC405GP supports the following debug modes, each of which supports a type of debug tool or
debug task commonly used in embedded systems development:
• Internal debug mode, which supports ROM monitors
• External debug mode, which supports JTAG debuggers
• Debug wait mode, which supports processor stopping or stepping for JTAG debuggers while
servicing interrupts
• Real-time trace mode, which supports trigger events for real-time tracing
Internal and external debug modes can be enabled simultaneously. Both modes are controlled by
fields in Debug Control Register 0 (DBCRO). Real-time trace mode is available only if internal,
external, and debug wait modes are disabled.
12.6.1 Internal Debug Mode
Internal debug mode provides access to architected processor resources and supports setting
hardware and software breakpoints and monitoring processor status. In this mode, debug events
generate debug interrupts, which can interrupt normal program flow so that monitor software can
collect processor status and alter processor resources.
Internal debug mode relies on exception handling software at a dedicated interrupt vector and an
external communications path to gebug software problems. This mode, used while the processor
executes instructions, enables debugging of operating system or application programs.
In this mode, debugger software is accessed through a communications port, such as
a
serial port,
external to the processor core.
To enable internal debug mode, the Debug Control Register 0 (DBCRO) field IDM is set to 1
(DBCRO[IDM]
=
1). To enable debug interrupts, MSR[DE]
=
1. A debug interrupt occurs on a debug
event only if DBCRO[IDM] = 1 and MSR[DE] = 1.
12.6.2 External Debug Mode
External debug mode provides access to architected processor resources and supports stopping,
starting, and stepping the processor, setting hardware and software breakpoints, and monitoring
processor status. In this mode, debug events cause the processor to become architecturally frozen.
While the processor is frozen, normal instruction execution stops and architected processor
resources can be accessed and altered. External bus activity continues in external debug mode.
The JTAG mechanism can pass instructions to the processor for execution, allowing a JTAG debugger
to display and alter processor resources, including memory.
The JTAG mechanism prevents the occurrence of a privileged exception when a privileged instruction
is executed while the processor is in user mode.
12-6 PPC405GP User's Manual
Preliminary