IBM PowerPC 405GP User Manual page 565

Embedded processor
Table of Contents

Advertisement

20.1.1.5 TX Channel Arbiter
The TX channel arbiter, connected to request lines from each TX channel, arbitrates between the TX
channels and decides which channel gains access to the TX common channel logic.
20.1.1.6 RX Channel Arbiter
The RX channel arbiter, connected to request lines from each RX channel, arbitrates between the RX
channels and decides which channel gains access to the RX common channel logic.
20.1.1.7 TX Common Channel Logic
The TX common channel logic is shared by all TX channels. It services a single TX channel at a time
(selected by the TX arbiter). This logic activates the PLS and OPS masters for data and buffer
descriptor transactions.
20.1.1.8 RX Common Channel Logic
The RX common channel logic is shared by all RX channels. It services a single RX channel at a time
(selected by the RX arbiter). This logic activates the PLS and OPS masters for data and buffer
descriptor transactions.
20.1.1.9 Register Map File
The register map file is used to configure MAL and read its status registers. Software accesses the
MAL register file using the
mtdcr
and
mfdcr
instructions.
20.2 Transmit and Receive Operations
The device driver is responsible for configuring MAL before a eOMMAe can begin requesting MAL to
process packets of data. The device driver should ensure that channels are not enabled during
reconfiguration; otherwise, fatal errors may occur.
For more information about the MAL software interface, see "MAL Programming Notes" on
page 20-18 .
20-4
. PPC405GP User's Manual
Preliminary

Advertisement

Table of Contents
loading

Table of Contents