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Figure 20-12. TX ChanneLActive Set Register (MALO_TXCASR)
0:1
Transmit Channel Active Set
Each bit represents its related
channel (bit 0 for channel 0, etc.) .
. When 1 is written to the bit, channel
operation is enabled.
There are only two TX channels in the
PPC405GP.
2:31
Reserved
10 112
3 1
1
Figure 20-13. TX ChanneLActive Reset Register (MALO_TXCARR)
0:1
Transmit Channel Active Reset
Each bit represents its related
channel (bit 0 for channel 0, etc.).
When 1 is written to the bit, channel
operation is disabled.
There are only two TX channels in the
PPC405GP.
2:31
Reserved
1
0
11
3 1
1
Figure 20-14. RX ChanneLActive Set Register (MALO_RXCASR)
0
Receive Channel Active Set
Each bit represents its related
channel (bit 0 for channel 0 etc.).
When 1 is written to the bit, channel
operation is enabled.
There is only one RX channel in the
PPC405GP.
1 :31
Reserved
.
Preliminary
Memory Access Layer
20-27
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