Table 10-3. Interrupt Handling Priorities - IBM PowerPC 405GP User Manual

All asynchronous interrupt types can be masked. In addition, certain synchronous interrupt types can
be masked.
Table 10-3. Interrupt Handling Priorities
Critical or
Priority Interrupt Type Noncritical
Causing Conditions
1 Machine check-data
Critical External bus error during data-side access
2 Debug-lAC Critical lAC debug event (in internal debug mode)
3
Machine check- Critical Attempted execution of instruction for which an external
instruction bus error occurred during fetch
4 Debug-EXC, UDE Critical
EXC or UDE debug event (in internal debug mode)
5
Critical interrupt input Critical Active level on the critical interrupt input
6
Watchdog timer-first Critical Posting of an enabled first time-out of the watchdog
time-out timer in the TSR
7
Instruction TLB Miss Noncritical Attempted execution of an instruction at an address
and process ID for which a valid matching entry was not
found in the TLB
8 Instruction storage - Noncritical
Instruction translati,on is active, execution access to the
ZPR[Zn] = 00 translated address is not permitted because
ZPR[Zn]
=
00 in user mode, and an attempt is made to
execute the instruction
9 Instruction storage - Noncritical
Instruction translation is active, execution access to the
TLB_entry[EX]
=
0
translated address is not permitted because
TLB_entry[EX]
=
0, and an attempt is made to execute
the instruction
Instruction storage - Noncritical Instruction translation is active, the page is marked
TLB_entry[G]
=
1
guarded, and an attempt is made to execute the
instruction
10 Program
Noncritical Attempted execution of illegal instructions, TRAP
instruction, privileged instruction in problem state
System call Noncritical Execution of the sc instruction
11
Data TLB miss Noncritical Valid matching entry for the effective address and
process ID of an attempted data access is not found in
the TLB
12 Data storage- Noncritical Data translation is active and data-side access to the
ZPR[Zn]
=
00 translated address is not permitted because
ZPR[Zn]
=
00 in user mode
13 Data storage- Noncritical
Data translation is active and write access to the
TLB_entry[WR] = 0 translated address is not permitted because
TLB_entry[WR]
=
0
Data storage- Noncritical Data translation is active and write access to the
TLB_entry[UO]
=
1 or translated address is not permitted because
SUOR[Un]
=
1 TLB_entry[UO]
=
1 or SUOR[Un]
=
1
14 Alignment Noncritical
dcbz to non-cachable address or write-through
storage; non-word aligned dcread, Iwarx, and stwcx,
as described in Table 10-13
15
Debug-BT, DAC, DVC, Critical BT, DAC, DVC, IC, TIE debug event (in internal debug
IC, TIE
mode) ,
Preliminary Interrupt Controller Operations
10-25