IBM PowerPC 405GP User Manual page 615

Embedded processor
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21
~6.3
Receiver DMA Mode
The UARTO Receive Enable field of the Chip Control Register 0, CPCO_CRO[DRE], controls the use
of the serial port receiver as a DMA source. For the receiver in DMA mode 0, when there is at least
one character in the RX FIFO or Receive Buffer Register, RBR, the DMA request goes active. Once
activated, the DMA request goes inactive when there are no more characters in the FIFO or RBA. For
the receiver in DMA mode 1, when the FIFOs are enabled and the trigger level or the timeout has
been reached, the DMA request goes active. Once activated, it will go inactive when there are no
more characters in the RX FIFO or RBR. To operate in this mode, DMA Channel Control Register 2
(DMAO_CR2) must be configured to accept DMA requests from an internal source. Setting the
Peripheral Location (PL) bit of DMAO_CR2 to a logic 1 configures DMA channel to accept DMA
requests from UARTO. Table 21-6 lists required register settings for UARTO receiver transfers. Other
DMA registers and register fields must be programmed appropriately, see Chapter 18, "Direct
Memory Access Controller," on page 18-1 for more information.
Table 21·6. UARTO Receiver DMA Mode Register Field Settings
Register [Field]
Meaning
CPCO_CRO[DRE]=1
UARTO DMA Receiver channel is enabled using DMA channel 2.
CPCO_CRO[DAEC]
Set to
°
to not clear CPCO_CRO[DRE] enable when terminal count is
reached, set to 1 to clear enable when terminal count is reached.
DMAO_CR2[TD]=1
DMA Channel 2 transfer direction is from peripheral to memory.
DMAO_CR2[PL]=1
DMA Channel 2 peripheral is on the OPB (UARTO).
DMAO_CR2[PW]=OO
Peripheral width is byte (8 bits).
DMAO_CR2[TM]=OO
DMA Channel 2 is in peripheral mode.
DMAO_CR3[PWC]=OOOO10
Peripheral Wait cycles, how long the internal DMAAck is active. Three
cycles are required.
DMAO_CR2[PHC]=OOO
Peripheral Hold Cycles are 0.
DMAO_CR2[ETD]=1
EOTfTC is programmed as terminal count output.
UARTO_FCR[DMS]
Set to
°
for a single DMA transfer or 1 for multiple DMA transfers.
Note:
When using DMA Channel 2 for UARTO receiver transfers, external DMA transfers cannot be
performed on this channel.
I
21·20
PPC405GP User's ivianuai
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