IBM PowerPC 405GP User Manual page 33

Figure 17-11. PMM 1 Local Address Register (PCILO_PMM1 LA) ............................................................. 17-23
Figure 17-12. PMM 1 Mask/Attribute Register (PCILO_PMM1 MA) ............................................................ 17-24
Figure 17-13. PMM 1 PCI Low Address Register (PCILO_PMM1 PCILA) .................................................. 17-24
Figure 17-14. PMM
°
High Address Register (PCILO_PMMOPCIHA) ........................................................ 17-25
Figure 17-15. PMM 2 Local Address Register (PCILO_PMM2LA) ............................................................. 17-25
Figure 17-16. PMM 2 Mask/Attribute Register (PCILO_PMM2MA) ............................................................ 17-26
Figure 17-17. PMM 2 Low Address Register (PCILO_PMM2PCILA) ......................................................... 17-26
Figure 17-18. PMM 2 PCI High Address Register (PCILO_PMM2PCIHA) ................................................. 17-27
Figure 17-19. PTM 1 Memory Size/Attribute Register (PCILO_PTM1MS) ................................................. 17-27
Figure 17-20. PTM 2 Local Address Register (PCILO_PTM1LA) ............................................................... 17-28
Figure 17-21. PTM 2 Memory Size/Attribute Register (PCILO_PTM2MS) ................................................. 17-28
Figure 17-22. PTM 2 Local Address Register (PCILO_PTM2LA) ............................................................... 17-29
Figure 17-23. PCI Configuration Address Register (PCICO_CFGADDR) .................................................. 17-30
Figure 17-24. PCI Configuration Data Register (PCICO_CFGDATA) ......................................................... 17-30
Figure 17-25. PCI Vendor ID Register (PCICO_VENDID) .......................................................................... 17-31
Figure 17-26. PCI Device ID Register (PCICO_DEVID) ............................................................................. 17-31
Figure 17-27. PCI Command Register (PCICO_CMD) ............................................................................... 17-32
Figure 17-28. PCI Status Register (PCICO_STATUS) ............................................................................... 17-33
Figure 17-29. PCI Revision ID Register (PCICO_REVID) .......................................................................... 17-35
Figure 17-30. PCI Class Register (PCICO_PCICLS) .................................................................................. 17-35
Figure 17-31. PCI Cache Line Size Register (PCICO_CACHELS) ............................................................. 17-36
Figure 17-32. PCI Latency Timer Register (PCICO_LATTIM) .................................................................... 17-36
Figure 17-33. PCI Header Type Register (PCICO_HDTYPE) .................................................................... 17-37
Figure 17-34. PCI Built-in Self Test Control Register (PCICO_BIST) ......................................................... 17-37
Figure 17-35. PCI PTM 1 BAR Register (PCICO_PTM1 BAR) .................... ; ............................................... 17-38
Figure 17-36. PCI PTM 2 BAR Register (PCICO_PTM2BAR) .................................................................... 17-39
Figure 17-37. PCI Subsystem Vendor ID Register (PCICO_SBSYSVID) ................................................... 17-39
Figure 17-38. PCI Subsystem ID Register (PCICO_SBSYSID) .................................................................. 17-40
Figure 17-39. PCI Capabilities Pointer (PCICO_CAP) ................................................................................ 17-40
Figure 17-40. PCllnterrupt Line Register (PCICO_INTLN) ........................................................................ 17-40
Figure 17-41. PCllnterrupt Pin Register (PCICO_INTPN) ......................................................................... 17-41
Figure 17-42. PCI Minimum Grant Register (PCICO_MINGNT) ................................................................. 17-41
Figure 17-43. PCI Maximum Latency Register (PCICO_MAXLTNCY) ....................................................... 17-41
Figure 17-44. PCI Interrupt Control/Status Register ................................................................................... 17-42
Figure 17-45. Error Enable Register (PCICO_ERREN) .............................................................................. 17-42
Figure 17-46. Error Status Register (PCICO_ERRSTS) ............................................................................. 17-43
Figure 17-47. Bridge Options 1 Register (PCICO_BRDGOPT1) ................................................................ 17-44
Figure 17-48. PLB Slave Error Syndrome Register
°
(PCICO_PLBBESRO) .............................................. 17-46
Figure 17-49. PLB Slave Error Syndrome 1 (PCICO_PLBBESR1) ............................................................ 17-47
Figure 17-50. PLB Slave Error Address Register (PCICO_PLBBEAR) ...................................................... 17-49
Figure 17-51. Capability Identifier (PCICO_CAPID) .................................................................................... 17-49
Figure 17-52. Next Item Pointer (PCICO_NEXTIPTR) ................................................................................ 17-49,
Figure 17-53. Power Management Capabilities Register (PCICO_PMC) ................................................... 17-50
Figure 17-54. Power Management Control/Status Register (PCICO_PMCSR) .......................................... 17-51
Figure 17-55. PMCSR PCI to PCI Bridge Support Extensions (PCICO_PMCSRBSE) .............................. 17-51
Figure 17-56. PCI Data (PCICO_DATA) ..................................................................................................... 17-52
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PPC405GP User's Manual Preliminary