IBM PowerPC 405GP User Manual page 194

7:12 TUN TUNE[5:0] Field Note: The tune bits adjust parameters that
control PLL jitter. The recommended
values minimize jitter for the PLL
implemented in the PPC405GP.
These bits are shown for information
only, and do not require modification
except in special clocking
circumstances, such as spread
spectrum clocking. For details on the
use of spread spectrum clock
generators (SSCGs) with the
PPC405GP, visit the technical
documents area of the IBM
PowerPC web site.
13:14 CBDV CPU:PLB Frequency Divisor
00 CPU:PLB divisor is 1
01 CPU:PLB divisor is 2
10 CPU:PLB divisor is 3
11 CPU:PLB divisor is 4
15:16
OPDV
OPB-PLB Frequency Divisor
00 OPB-PLB divisor is 1
01 OPB-PLB divisor is 2
10 OPB-PLB divisor is 3
11 OPB-PLB divisor is 4
17:18 PPDV PCI-PLB Frequency Divisor See "PC I Clocks" on page 7-8 for details
00 PCI-PLB divisor is 1 regarding asynchronous PCI clocking and
01 PCI-PLB divisor is 2 how it relates to synchronous clocking.
10 PCI-PLB divisor is 3
11 PCI-PLB divisor is 4
19:20 EPDV External Bus-PLB Frequency Divisor
00 External bus-PLB divisor ratio is 2:1
01 External bus-PLB divisor ratio is 3:1
10 External bus-PLB divisor ratio is 4:1
11 External bus-PLB divisor ratio is 5: 1
21 :31 Reserved
7.7.2 Chip Control Register 0 (CPCO_CRO)
Only GPGO_GRO fields related to clocking are shown in Figure 7-3. GPGO_GRO
O : 23 ,
which control
GPID and UART functions, are summarized in "GPGO_GRO" on page 25-17.
Preliminary Clocking
7-11