IBM PowerPC 405GP User Manual page 613

23 DAEC DMA Allow Enable Clear for UARTO
o
DTE and ORE for UARTO are not cleared
when the UART receives a corresponding
terminal count.
1 DTE and ORE for UARTO are cleared
when the UART receives a corresponding
terminal count.
24 UOEC Select External Clock for UARTO
o
UARTO uses the internally derived serial
clock.
1 UARTO uses the UARTSerClk external
serial clock input.
25 U1EC
Select External Clock for UART1
o
UART1 uses the internally derived serial
clock.
1 UART1 uses the UARTSerClk external
serial clock input.
26:30 UDIV UART Divisor UDIV specifies the divider ratio between the
00000 Divide by 1 CPU and UART serial clock frequencies.
00001 Divide by 2
UARTO and UART1 can use a serial clock
00010 Divide by 3 frequency derived from the CPU clock
frequency divided by UDIV, or use the
UARTSerClk external serial clock input. For
example, if the CPU runs at 200M Hz, a
11110 Divide by 31
UDIV of 20 sets the serial clock frequency at
11111 Divide by 32
10MHz.
Note: Maximum serial clock frequency is
slightly less than 1/2x OPB frequency .
31
.
,
Reserved.
...
21.6.2 Transmitter DMA Mode
The UARTO Transmit Channel Enable field of the Chip Control Register 0, CPCO_CRO[DTE], controls
the use of the serial port transmitter as a DMA destination. For the transmitter in DMA mode 0, when
the FIFOs are disabled or the FIFOs are enabled and there are no characters in the TX FIFO or
Transmit Holding Register (THR), the DMA request goes active. Once activated,· the DMA request
goes inactive after the first character is loaded into the TX FIFO or THR. For the transmitter in DMA
mode 1, when FIFOs are enabled and there is at least one unfilled position in the TX FIFO, the DMA
request goes active. This signal will become inactive when the TX FIFO is completely full. To operate
in this mode, DMA Channel Control Register 3 (DMAO_CR3) must be configured to accept DMA
requests from an internal source. Setting the Peripheral Location (PL) bit of DMAO_CR3 to a logic 1
configures DMA channel to accept DMA requests from UARTO. Table 21-5 lists required register
21-18 PPC405GP Use(s Manual
Preliminary