Burst Transactions - IBM PowerPC 405GP User Manual

16.3 Burst Transactions
Bursting is controlled on a per-bank basis by the Burst Mode Enable bit in the EBCO_BnAP registers.
When enabled (EBCO_BnAP[BME]=1) this mode activates bursting for all cache line fills and flushes,
PLB burst transfers to the EBC, and all packing and unpacking operations. When bursting is enabled:
• P8rCSn
becomes active 0-3 (EBCO_BnAP[CSN]) PerClk cycles after the address becomes valid.
• PerCSn is no longer actively driven:
- 1-32 (EBCO_BnAP[FWT]+ 1) PerClk cycles after the address becomes valid when a single
transfer occurs to a burst-enabled bank.
- 1-8 (EBCO_BnAP[BWT]+ 1) PerClk cycles after the last address becomes valid during a burst:
- If EBCO_CFG[CSTC]=1 or EBCO_BnAP[TH]>O, PerCSn is driven high.
- If EBCO_CFG[CSTC]=O and EBCO_BnAP[TH]=O, PerCSn transitions directly from logic
°
to
the high-impedance state.
• During read operations PerOE is driven low 0-3 (EBCO_BnAP[OEN]) PerClk cycles after PerCSn is
active. PerOE goes inactive when PerCSn goes inactive.
• For bursts, the EBC drives a new address (EBCO_BnAP[FWT]+1) + N*(EBCO_BnAP[BWT]+1)
cycles after the start of the transaction, where N = 0, 1, 2, ...
• Addresses during a burst may "wrap:' For example, cache line fills are processed critical word first.
• During write operations, the write data is driven concurrent with each address.
• PerWBEO:3 can be either write byte enables or read and write enables.
If EBCO_BnAP[BEM]=O, PerWBEO:3 are write byte enables and:
- For the first transfer of a burst, or a single transfer to a burst enabled bank, the appropriate write
byte enables go low 0-3 (EBCO_BnAP[WBN]) cycles after PerCSn becomes active. The EBC
then waits until EBCO_BnAP[FWT] - EBCO_BnAP[WBF] + 1 cycles have elapsed since the start
of the transaction and drives PerWBEO:3 inactive.
- The remaining transfers of the burst are similar, except that PerWBEO:3 becomes active
EBCO_BnAP[WBN] cycles after each new address is driven on the interface. The PerWBEO:3
remain low for (EBCO_BnAP[BWT] + 1) - EBCO_BnAP[WBN] - EBCO_BnAP[WBF] cycles.
If EBCO_BnAP[BEM]=1, PerWBEO:3 are byte enables that have timing identical to the peripheral
address bus. In this case the EBCO_BnAP[WBN] and EBCO_BnAP[WBF] parameters are ignored.
• PerBLast is active throughout the entire last (or only) transfer of a burst operation and is
deactivated during the programmed hold time (EBCO_BnAP[TH]).
• Access bank parameters CSN and OEN apply to the first (or only) transfer of a burst, while WBN
and WBF apply to all transfers. It is required that FWT
~
CSN + MAX(OEN,WBN) + WBF and
BWT
~
WBN+WBF.
• Hold time (EBCO_BnAP[TH]) is programmable from
°
to 7 cycles. During the hold time, the
peripheral address bus remains driven and all control signals are driven inactive. If the operation
was a write, the peripheral data bus continues driving the write data.
• There is no guarantee of dead cycles between transfers on the peripheral interface. If there are
back-to-back transfers to the same memory bank and the number of hold cycles is programmed to
zero (EBCO_BnAP[TH]=O) and EBCO_BnAP[CSN]=O, then:
16-8
PPC405GP User's Manual