IBM PowerPC 405GP User Manual page 663

sthux 24-163
sthx 24-164
stmw 24-165
storage attribute control registers
DCCR 6-19
DCWR 6-18
ICCR 6-19
SGR 6-19
SLER 6-19
SUOR 6-19
storage attributes
caching inhibited (I)
real mode 6-19
virtual mode 6-5
endian (E)
and little endian 3-30
real mode 6-19
when controlled by TLB 6-6
guarded (G)
controlling speculative accesses 3-37
real mode 6-19
virtual mode 6-6
memory coherent (M)
not supported 6-6
overview 3-3
real mode 6-17
TLB control of 6-5
user-defined (UO)
real mode 6-19
virtual mode 6-5
write-through (W)
real mode 6-18
virtual mode 6-5
Storage Guarded Register. See SGR
Storage Guarded Register. See SGR
Storage Little Endian Register ~ See SLER
storage reference instructions 3-48
storage regions
big endian
alignment 3-27
byte-reverse instructions 3-32- 3-33
little endian
accessing data from 3-31
alignment 3-27
byte reversal 3-31
byte-reverse instructions 3-32- 3-33
data alignment 3-32
fetching instructions from 3-31
storage synchronization 3-46
Storage User-Defined 0 Register.
See
SUOR
string instructions
access protection 6-16
structure mapping
examples 3-29
stswi 24-166
stswx 24-167
stw 24-169
stwbrx 24-170
stwcx. 24-171
stwu 24-173
stwux 24-174
X-18
PPC405GP User's Manual
stwx 24-175
SUOR 25-233
SUOR (Storage User-Defined 0 Register)
controlling the user-defined (UO) storage attribute
6-19
sub 24-176
sub. 24-176
subc 24-177
subc. 24-177
subco 24-177
subco. 24-177
subf 24-176
subf. 24-176
subfc 24-177
subfc. 24-177
subfco 24-177
subfco. 24-177
subfe 24-178
subfe. 24-178
subfeo 24-178
subfeo. 24-178
subfic 24-179
subfme 24-180
subfme. 24-180
subfmeo 24-180
subfmeo. 24-180
subfo 24-176
subfo. 24-176
subfze 24-181
subfze. 24-181
subfzeo 24-181
subfzeo. 24-181
subi 24-9
subic 24-10
subic. 24-11
subis 24-12
subo 24-176
subo. 24-176
supervisor state. See privileged mode
sync 24-182
storage synchronization 3-46
synchronization
context 3-44
execution, defined 3-46
ICU 4-5
references to PowerPC Architecture 3-43
storage 3-46
synchronous interrupts 10-22
system call interrupts
register settings 10-41
T
TBL 25-235
tblrehi 24-185
tblrelo 24-185
tblwehi 24-189
tblwelo 24-189
TBU 25-236
TCR 11-9, 25-237
TID (translation ID)
and MMU access protection
time base 11-2
Preliminary