IBM PowerPC 405GP User Manual page 644

23.5 GPIO Register Overview
The following table contains a summary of the GPIO registers.
Table 23-2. GPIO Register Summary
MMIO Address Mnemonic Description Access Mode
EF600700
GPIOO_OR GPIO Output RIW
EF600704
GPIOO_TCR GPIO Three-State Control RIW
EF600718
GPIOO_ODR GPIO Open Drain RIW
EF60071C
GPIOO_IR GPIO Input R
Note: All GPIO registers are memory-mapped and accessed via load/store instructions at the address of the
register.
23.5.1 GPIO Register Reset Values
When a system reset occurs, each register in the GPIO macro, except GPIOO_IR, is reset to 0. All
outputs are in the high-impedance state. GPIOO_IR is not reset because it is always clocked and
always follows the GPIO_ln state.
23.5.2 Detailed Register Description
The following sections provide a bit description of the GPIO registers. All registers are accessed from
the OPB. The GPIOO_IR register is read-only; all other registers are both read and write accessible.
Figure 23-3. GPIO Registers
0
Reserved
1:23 GPIO register bits
24:31 Reserved
23.5.2.1 GPIO Output Register (GPIOO_OR)
The state of each bit in the GPIOO_OR Register may be reflected in the corresponding GPIO
Controller macro output signal GPIO_Out.
23.5.2.2 GPIO Three-State Control Register (GPIOO_ TCR)
Each bit in the GPIOO_ TCR Register controls the corresponding GPIO_ TS_Control macro output
signal.Each bit in the GPIOO_ TCR Register controls the corresponding GPIO_ TS_Control macro
output signal.
When 0, GPIO-:-TS_Control forces the module I/O drivers into the high-impedance state.
31
1
Preliminary GPIO Operations 23-5