Handling Writes From Pci Masters; Miscellaneous - IBM PowerPC 405GP User Manual

Byte Enable Handling
PCI byte enables are treated as don't cares for PCI reads. The PCI bridge performs doubleword burst
or single-beat doubleword reads on the PLB, regardless of the byte enables presented by the
requesting PCI master.
Note:
This rule assumes that all PLB memory is prefetchable and that all PLB memory accesses are
nondestructive.
17.4.2.3 Handling Writes from PCI Masters
PCI bridge responds to Memory Write and Memory Write and Invalidate commands. All PCI master
writes are posted. A 64-byte write buffer is used for this purpose. The write buffer accepts up to two
separate PCI write transactions. Two single-beat writes, one burst write, or a combination of a single-
beat and a burst writes can be posted. If the write buffer is full, new writes are retried until buffer
space becomes available.
Note:
The maximum of two posted transactions is as viewed from the PCI master. The number of
writes performed on the PLB can be more than two, depending on the setting of byte enables
of write burst data. See "Byte Enable Handling" on page 17-17.
The PCI bridge begins a PLB write request as soon as a PCI master write has completed on the PCI
bus, or a bursting PCI master has written at least six words of data. The PCI bridge continues to
receive data from a bursting PCI master as it transfers data to the PLB. If the write post buffer fills, the
PCI master is target disconnected. If the write post buffer empties, the PLB cycle is master
terminated.
Writes are executed in the same order they are received.
Byte Enable Handling
The PLB does not support non-contiguous byte enables, whereas the PCI bus does. The PLB
supports the use of byte enables only for non-line, non-burst transactions, whereas the PCI bus
supports any combination of byte enables for any data phase. Therefore, when a PCI master presents
a data phase without all byte enables asserted, the bridge disconnects and treats that data phase as
one or two single-beat writes on PLB, depending on whether or not byte enables are non-contiguous.
Masters presenting writes without all byte enables asserted experience degraded performance.
17.4.2.4 Miscellaneous
The PCI target forces single-beat transfers when reserved burst or cache line wrap order is used.
The PCI target causes master abort of reserved command encodings, and does not respond to lID,
interrupt
ackn~wledge,
or special cycle commands.
The PLB master does not abort requests.
Preliminary PCllnterface
17-17