IBM PowerPC 405GP User Manual page 631

I~
I
DIV6
I
Divisor bit 6
DIV7 Divisor bit 7
IICO_CLKDIV divides PPC405GP's on-chip peripheral bus (OPS) clock to form the base clock for the
IIC bus.
Table 22-4 lists the divisor values for several OPS frequency ranges. These divisor values apply for
standard and fast mode. Select the divisor value by matching the OPS clock frequency to the
corresponding frequency range in Table 22-4. For example, if the OPS clock frequency is 50MHz,
select a divisor value of Ox4.
Table 22-4. IICO Clock Divide Programming
Divisor
OPB Frequency Range (MHz) Value
20
Ox1
20
<
(:5
30 Ox2
30
<
(:5
40 Ox3
40
<
(:5
50 Ox4
50
<
(:5
60 Ox5
22.3.12 lIeo Interrupt Mask Register
The IICO Interrupt Mask Register (IICO_INTRMSK) specifies which conditions can generate an IIC
interrupt when the IIC interrupt is enabled, IICO_MDCNTL[EINT]=1.
Figure 22-15 illustrates the IICO_INTRMSK.
EIRC EIWC EIHE EITA
... ... ...
...
10111213141516171
t t t t
EWCS EIWS EIIC EIMTC
Figure 22-15. IICO Interrupt Mask Register (IICO_INTRMSK)
0
·EIRC
Enable IRQ on Slave Read Complete The interrupt is activated upon receipt of a
o
Disable
Stop during a slave read on the IIC bus.
1 Enable
IICO_XTCNTLSS[SRC]
=
1 indicates a
Slave Read Complete.
1 EIRS
Enable IRQ on Slave Read Needs Service The interrupt is activated upon receipt of a
o
Disable
slave read on the IIC bus and the slave
1 Enable
buffer was empty or went empty and more
data was requested on the IIC bus.
Note: IICO_XTCNTLSS[SRS]
=
1
indicates a Slave Read Needs
Service.
22-16
PPC405GP User's Manual
Preliminary