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3.3.1
General Purpose Registers (RO-R31)
The PPC405GP contains thirty-two 32-bit general purpose registers (GPRs). Data from memory can
be read into GPRs using load instructions and the contents of GPRs can be written to memory using
store instructions. Most integer instructions use GPRs for source and destination operands. See
Table 25-1, "PPC405GP General Purpose Registers," on page 25-1 for the numbering of the GPRs.
1
0
31
1
Figure 3-2. General Purpose Registers (RO-R31)
I
0:31
I
General Purpose Register data
3.3.2
Special Purpose Registers
Special purpose registers (SPRs), which are part of the PowerPC Architecture and the IBM PowerPC
Embedded Environment, are accessed using the mtspr and mfspr instructions.
SPRs control the operation of debug facilities, timers, interrupts, storage control attributes, and other
architected processor resources. Table 25-2, "Special Purpose Registers," on page 25-2 shows the
mnemonic, name, and number for each SPR. Table 3-2, "PPC405GP SPRs," on page 3-7 lists the
PPC405GP SPRs by function and indicates the pages where the SPRs are described more fully.
Except for the Link Register (LR), the Count Register (CTR), the Fixed-point Exception Register
(XER), User SPR General 0 (USPRGO, and read access to SPR General 4-7 (SPRG4-SPRG7), all
SPRs are privileged. As SPRs, the registers TBL and TBU are privileged write-only; as TBRs, these
registers can be read in user mode. Unless used to access non-privileged SPRs, attempts to execute
mfspr and mtspr instructions while in user mode cause privileged violation program interrupts. See
"Privileged SPRs" on page 3-42.
3-6
PPC405GP User's Manual
Preliminary
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