Tlb Management - IBM PowerPC 405GP User Manual

• In supervisor state
- Data store, dcbi, dcbz, or dccci to an EA having TLB_entry[WR]
=
0 and ZPR[Zn] other than 11
or 10.
dcba does not cause data storage exceptions. If conditions occur that would otherwise cause such an
exception, dcba is treated as a no-op.
"Zone Protection" on page 6-13 describes zone protection in detail. See "Data Storage Interrupt" on
page 10-36 for a detailed discussion of the data storage interrupt.
6.4.2 Instruction Storage Interrupt
An instruction storage interrupt is generated when instruction address translation is active and the
processor attempts to execute an instruction at an EA for which fetch access is not permitted, for any
of the following reasons:
• In the problem state
- Instruction fetch from an EA with ZPR[Zn]
=
00.
- Instruction fetch from an EA having TLB_entry[EX] = 0 and ZPR[Zn]
:f::
11.
- Instruction fetch from an EA having TLB_entry[G]
=
1.
• In the supervisor state
- Instruction fetch from an EA having TLB_entry[EX]
=
0 and ZPR[Zn] other than 11 or 10.
- Instruction fetch from an EA having TLB_entry[G]
=
1.
See "Zone Protection" on page 6-13 for a detailed discussion of zone protection. See "Instruction
Storage Interrupt" on page 10-38 for a detailed discussion of the instruction storage interru·pt.
6.4.3 Data TLB Miss Interrupt
A data TLB miss interrupt is generated if data address translation is enabled and a valid TLB entry
matching the EA and PID is not present. The interrupt applies to data access instructions and cache
operations (excluding cache touch instructions).
See "Data TLB Miss Interrupt" on page 10-43 for a detailed discussion.
6.4.4 Instruction TLB Miss Interrupt
The instruction TLB miss interrupt is generated if instruction address translation is enabled and
execution is attempted for an instruction for which a valid TLB entry matching the EA and PID for the
instruction fetch is not present.
See "Instruction TLB Miss Interrupt" on page 10-44 for a detailed discussion.
6.5 TLB Management
The processor does not imply any format for the page tables or the page table entries because there'
is no hardware support for page table management. Software has complete flexibility in ,implementing
a replacement strategy, because software does the replacing. For example, software can "lock" TLB
6-10
PPC405GP User's Manual Preliminary