Machine Check Interrupts; Instruction Machine Check Handling; Table 10-7. Register Settings During Critical Input Interrupts - IBM PowerPC 405GP User Manual

Executing an rfci instruction restores the program counter from SRR2 and the MSR from SRR3, and
execution resumes at the address in the program counter.
Table 10-7. Register Settings during Critical Input Interrupts
SRR2 Written with the address of the next instruction to be executed
SRR3 Written with the contents of the MSR
MSR WE, CE, EE, PR, OWE, OE,IR, OR~O
ME~ unchanged
PC EVPR[O:15] II Ox0100
10.13 Machine Check Interrupts
When an external bus error occurs on an instruction fetch, and execution of that instruction is
subsequently attempted, a machine check-instruction interrupt occurs.
When an external bus error occurs while attempting data accesses, a machine check-data interrupt
occurs.
When an instruction-side machine check interrupt occurs, the PPC405GP stores the address of the
excepting instruction in SRR2. When a data-side machine check occurs, the PPC405GP stores the
address of the next sequential instruction in SRR2. Simultaneously, for all machine check interrupts,
the contents of the MSR are loaded into SRR3.
The MSR Machine Check Enable bit (MSR[ME]) is reset to 0 to disable another machine check from
interrupting the machine check interrupt handling routine. The other MSR bits are loaded with the
values shown in Table 10-8, "Register Settings during Machine Check-Instruction Interrupts," on
page 10-36 and Table 10-9, "Register Settings during Machine Check-Data Interrupts," on
page 10-36. The high-order 16 bits of the program counter are then written with the contents of the
EVPR and the low-order 16 bits of the program counter are written with Ox0200. Interrupt processing
begins at the new address in the program counter.
Executing an rfci instruction restores the program counter from SRR2 and the MSR from SRR3, and
execution resumes at the address in the program counter.
10.13.1 Instruction Machine Check Handling
When a machine check occurs on an instruction fetch, and execution of that instruction is
subsequently attempted, a machine check-instruction interrupt occurs. If enabled by MSR[ME], the
processor reports the machine check-instruction interrupt by vectoring to the machine check
handler (EVPR[0:15] II Ox0200), setting ESR[MCI]. Note that only a bus error can cause a machine
check-instruction interrupt. Taking the vector automatically clears MSR[ME] and the other MSR
fields.
Note that it is improper to declare a machine check-instruction interrupt when the instruction is
fetched, because the address is possibly the result of an incorrect speculation by the fetcher. It is
quite likely that no attempt will be made to execute an instruction from the erroneous address. The
interrupt will occur only if execution of the instruction is subsequently attempted.
When a machine check occurs on an instruction fetch, the erroneous instruction is never validated in
the instruction cache unit (ICU). Fetch requests to cachable memory that miss in the ICU cause an
instruction cache line fill (eight words). If any words in the fetched line are associated with an error, an
Preliminary
Interrupt Controller Operations 10-35