Table of Contents
Advertisement
15.6.3 Sleep Mode Exit
The power management wake-up logic monitors the PLB for SDRAM reads or writes from other
masters. In addition, the wakeup logic also monitor the DCR bus for accesses to SDRAM
configuration and status registers. If either a PLB or DCR operation targeting the SDRAM controller is
detected the SDRAM controller wakes up. The wakeup process results in a two cycle additional
latency to the pending operation.
SDRAM Controller
15-21
Advertisement
Chapters
Table of Contents
